From 83dc1c9705b82b30b7f08df027ae9e1f4696e0d3 Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Fri, 1 Dec 2023 22:40:27 -0800
Subject: [PATCH] riscv: Add detect flags, not detected yet.

---
 Common/CPUDetect.h        |  5 +++++
 Common/RiscVCPUDetect.cpp |  5 +++++
 Common/RiscVEmitter.cpp   | 12 ++++--------
 3 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/Common/CPUDetect.h b/Common/CPUDetect.h
index db1ea377a5..939e3044a9 100644
--- a/Common/CPUDetect.h
+++ b/Common/CPUDetect.h
@@ -114,6 +114,11 @@ struct CPUInfo {
 	bool RiscV_Zbb;
 	bool RiscV_Zbc;
 	bool RiscV_Zbs;
+	bool RiscV_Zcb;
+	bool RiscV_Zfa;
+	bool RiscV_Zfh;
+	bool RiscV_Zfhmin;
+	bool RiscV_Zicond;
 
 	// LoongArch specific extension flags.
 	bool LOONGARCH_CPUCFG;
diff --git a/Common/RiscVCPUDetect.cpp b/Common/RiscVCPUDetect.cpp
index 5f18db8cd9..11fe5f9cdf 100644
--- a/Common/RiscVCPUDetect.cpp
+++ b/Common/RiscVCPUDetect.cpp
@@ -245,6 +245,11 @@ std::vector<std::string> CPUInfo::Features() {
 		{ RiscV_Zbb, "Bitmanip Zbb" },
 		{ RiscV_Zbc, "Bitmanip Zbc" },
 		{ RiscV_Zbs, "Bitmanip Zbs" },
+		{ RiscV_Zcb, "Compress Zcb" },
+		{ RiscV_Zfa, "Float Additional" },
+		{ RiscV_Zfh, "Float Half" },
+		{ RiscV_Zfhmin, "Float Half Minimal" },
+		{ RiscV_Zicond, "Integer Conditional" },
 		{ RiscV_Zicsr, "Zicsr" },
 		{ CPU64bit, "64-bit" },
 	};
diff --git a/Common/RiscVEmitter.cpp b/Common/RiscVEmitter.cpp
index 936ee4da77..f7bc484c03 100644
--- a/Common/RiscVEmitter.cpp
+++ b/Common/RiscVEmitter.cpp
@@ -32,8 +32,7 @@ static inline bool SupportsCompressed(char zcx = '\0') {
 		return false;
 
 	switch (zcx) {
-	// TODO: cpu_info.RiscV_Zcb
-	case 'b': return false;
+	case 'b': return cpu_info.RiscV_Zcb;
 	case '\0': return true;
 	default: return false;
 	}
@@ -79,18 +78,15 @@ static inline bool SupportsBitmanip(char zbx) {
 }
 
 static inline bool SupportsIntConditional() {
-	// TODO: cpu_info.RiscV_Zicond;
-	return false;
+	return cpu_info.RiscV_Zicond;
 }
 
 static inline bool SupportsFloatHalf(bool allowMin = false) {
-	// TODO
-	return false;
+	return cpu_info.RiscV_Zfh || (cpu_info.RiscV_Zfhmin && allowMin);
 }
 
 static inline bool SupportsFloatExtra() {
-	// TODO: cpu_info.RiscV_Zfa
-	return false;
+	return cpu_info.RiscV_Zfa;
 }
 
 enum class Opcode32 {