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jit: Avoid a super unlikely write to zero.

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Unknown W. Brackets 2015-04-07 18:20:37 -07:00
parent 8afab3f94f
commit 788b9d78f8
4 changed files with 5 additions and 4 deletions
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2
Core/MIPS/ARM/ArmCompBranch.cpp
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@ -509,7 +509,7 @@ void ArmJit::Comp_JumpReg(MIPSOpcode op)
}
MIPSGPReg rs = _RS;
MIPSGPReg rd = _RD;
bool andLink = (op & 0x3f) == 9;
bool andLink = (op & 0x3f) == 9 && rd != MIPS_REG_ZERO;
MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);

2
Core/MIPS/ARM64/Arm64CompBranch.cpp
View file

@ -489,7 +489,7 @@ void Arm64Jit::Comp_JumpReg(MIPSOpcode op)
}
MIPSGPReg rs = _RS;
MIPSGPReg rd = _RD;
bool andLink = (op & 0x3f) == 9;
bool andLink = (op & 0x3f) == 9 && rd != MIPS_REG_ZERO;
MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);

1
Core/MIPS/MIPSInt.cpp
View file

@ -298,6 +298,7 @@ namespace MIPSInt
DelayBranchTo(addr);
break;
case 9: //jalr
if (rd != 0)
R(rd) = PC + 8;
DelayBranchTo(addr);
break;

2
Core/MIPS/x86/CompBranch.cpp
View file

@ -670,7 +670,7 @@ void Jit::Comp_JumpReg(MIPSOpcode op)
}
MIPSGPReg rs = _RS;
MIPSGPReg rd = _RD;
bool andLink = (op & 0x3f) == 9;
bool andLink = (op & 0x3f) == 9 && rd != MIPS_REG_ZERO;
MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);