From 788b9d78f8d2cad1fce1ae87eedb982c7e8cabfd Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Tue, 7 Apr 2015 18:20:37 -0700 Subject: [PATCH] jit: Avoid a super unlikely write to zero. --- Core/MIPS/ARM/ArmCompBranch.cpp | 2 +- Core/MIPS/ARM64/Arm64CompBranch.cpp | 2 +- Core/MIPS/MIPSInt.cpp | 3 ++- Core/MIPS/x86/CompBranch.cpp | 2 +- 4 files changed, 5 insertions(+), 4 deletions(-) diff --git a/Core/MIPS/ARM/ArmCompBranch.cpp b/Core/MIPS/ARM/ArmCompBranch.cpp index 15fbe5684b..be067e1e74 100644 --- a/Core/MIPS/ARM/ArmCompBranch.cpp +++ b/Core/MIPS/ARM/ArmCompBranch.cpp @@ -509,7 +509,7 @@ void ArmJit::Comp_JumpReg(MIPSOpcode op) } MIPSGPReg rs = _RS; MIPSGPReg rd = _RD; - bool andLink = (op & 0x3f) == 9; + bool andLink = (op & 0x3f) == 9 && rd != MIPS_REG_ZERO; MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4); bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs); diff --git a/Core/MIPS/ARM64/Arm64CompBranch.cpp b/Core/MIPS/ARM64/Arm64CompBranch.cpp index 2a222f3f28..9f1b2ad05a 100644 --- a/Core/MIPS/ARM64/Arm64CompBranch.cpp +++ b/Core/MIPS/ARM64/Arm64CompBranch.cpp @@ -489,7 +489,7 @@ void Arm64Jit::Comp_JumpReg(MIPSOpcode op) } MIPSGPReg rs = _RS; MIPSGPReg rd = _RD; - bool andLink = (op & 0x3f) == 9; + bool andLink = (op & 0x3f) == 9 && rd != MIPS_REG_ZERO; MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4); bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs); diff --git a/Core/MIPS/MIPSInt.cpp b/Core/MIPS/MIPSInt.cpp index a3012cad1f..8c82e4b7a8 100644 --- a/Core/MIPS/MIPSInt.cpp +++ b/Core/MIPS/MIPSInt.cpp @@ -298,7 +298,8 @@ namespace MIPSInt DelayBranchTo(addr); break; case 9: //jalr - R(rd) = PC + 8; + if (rd != 0) + R(rd) = PC + 8; DelayBranchTo(addr); break; } diff --git a/Core/MIPS/x86/CompBranch.cpp b/Core/MIPS/x86/CompBranch.cpp index 8aad20ed3b..9b7d999b8c 100644 --- a/Core/MIPS/x86/CompBranch.cpp +++ b/Core/MIPS/x86/CompBranch.cpp @@ -670,7 +670,7 @@ void Jit::Comp_JumpReg(MIPSOpcode op) } MIPSGPReg rs = _RS; MIPSGPReg rd = _RD; - bool andLink = (op & 0x3f) == 9; + bool andLink = (op & 0x3f) == 9 && rd != MIPS_REG_ZERO; MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4); bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);