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fix Jit

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This commit is contained in:
Ced2911 2013-08-19 09:48:12 +02:00
parent 3350061197
commit 52f4cccfa4
3 changed files with 6 additions and 8 deletions
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8
Core/MIPS/PPC/PpcCompBranch.cpp
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@ -59,6 +59,7 @@ void Jit::BranchRSRTComp(u32 op, PpcGen::FixupBranchType cc, bool likely)
if (!likely && delaySlotIsNice)
CompileDelaySlot(DELAYSLOT_NICE);
if (gpr.IsImm(rt) && gpr.GetImm(rt) == 0)
{
gpr.MapReg(rs);
@ -87,12 +88,10 @@ void Jit::BranchRSRTComp(u32 op, PpcGen::FixupBranchType cc, bool likely)
else
{
FlushAll();
ptr = B_Cond(cc);
ptr = B_Cond(cc);
CompileDelaySlot(DELAYSLOT_FLUSH);
}
INFO_LOG(CPU, "targetAddr: %08x,js.compilerPC: %08x offset: %08x, op: %08x\n", targetAddr, js.compilerPC, offset, op);
// Take the branch
WriteExit(targetAddr, 0);
@ -143,7 +142,6 @@ void Jit::BranchRSZeroComp(u32 op, PpcGen::FixupBranchType cc, bool andLink, boo
// Take the branch
if (andLink)
{
//Break();
MOVI2R(SREG, js.compilerPC + 8);
STW(SREG, CTXREG, MIPS_REG_RA * 4);
}
@ -339,7 +337,6 @@ void Jit::Comp_Jump(u32 op) {
break;
case 3: //jal
//Break();
gpr.MapReg(MIPS_REG_RA, MAP_NOINIT | MAP_DIRTY);
MOVI2R(gpr.R(MIPS_REG_RA), js.compilerPC + 8);
CompileDelaySlot(DELAYSLOT_NICE);
@ -393,7 +390,6 @@ void Jit::Comp_JumpReg(u32 op) {
break;
case 9: //jalr
// mips->reg = js.compilerPC + 8;
//Break();
MOVI2R(SREG, js.compilerPC + 8);
STW(SREG, CTXREG, MIPS_REG_RA * 4);
break;

2
Core/MIPS/PPC/PpcJit.cpp
View file

@ -31,6 +31,7 @@ void Jit::CompileDelaySlot(int flags)
// Save flags register
MOVI2R(SREG, (u32)&delaySlotFlagsValue);
STW(FLAGREG, SREG);
MFCR(R19);
}
js.inDelaySlot = true;
@ -45,6 +46,7 @@ void Jit::CompileDelaySlot(int flags)
// Restore flags register
MOVI2R(SREG, (u32)&delaySlotFlagsValue);
LWZ(FLAGREG, SREG);
MTCR(R19);
}
}

4
Core/MIPS/PPC/PpcRegCache.cpp
View file

@ -50,7 +50,7 @@ const PPCReg *PpcRegCache::GetMIPSAllocationOrder(int &count) {
// R9 and upwards are reserved for jit basics.
if (options_->downcountInRegister) {
static const PPCReg allocationOrder[] = {
/*R14, R15, R16, R17, R18, */R19,
/*R14, R15, R16, R17, R18, R19,*/
R20, R21, R22, R23, R24, R25,
R26, R27, R28, R29, R30, R31,
};
@ -58,7 +58,7 @@ const PPCReg *PpcRegCache::GetMIPSAllocationOrder(int &count) {
return allocationOrder;
} else {
static const PPCReg allocationOrder2[] = {
/*R14, R15, R16, R17, R18,*/ R19,
/*R14, R15, R16, R17, R18, R19,*/
R20, R21, R22, R23, R24, R25,
R26, R27, R28, R29, R30, R31,
};