From 52f4cccfa40d5dce29e04857e3a52d4a566a6179 Mon Sep 17 00:00:00 2001
From: Ced2911 <Ced2911@gmail.com>
Date: Mon, 19 Aug 2013 09:48:12 +0200
Subject: [PATCH] fix Jit

---
 Core/MIPS/PPC/PpcCompBranch.cpp | 8 ++------
 Core/MIPS/PPC/PpcJit.cpp        | 2 ++
 Core/MIPS/PPC/PpcRegCache.cpp   | 4 ++--
 3 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/Core/MIPS/PPC/PpcCompBranch.cpp b/Core/MIPS/PPC/PpcCompBranch.cpp
index 10b959a098..b594e1ab29 100644
--- a/Core/MIPS/PPC/PpcCompBranch.cpp
+++ b/Core/MIPS/PPC/PpcCompBranch.cpp
@@ -59,6 +59,7 @@ void Jit::BranchRSRTComp(u32 op, PpcGen::FixupBranchType cc, bool likely)
 	if (!likely && delaySlotIsNice)
 		CompileDelaySlot(DELAYSLOT_NICE);
 
+
 	if (gpr.IsImm(rt) && gpr.GetImm(rt) == 0)
 	{
 		gpr.MapReg(rs);
@@ -87,12 +88,10 @@ void Jit::BranchRSRTComp(u32 op, PpcGen::FixupBranchType cc, bool likely)
 	else
 	{
 		FlushAll();
-		ptr = B_Cond(cc);
+		ptr = B_Cond(cc);		
 		CompileDelaySlot(DELAYSLOT_FLUSH);
 	}
 
-	INFO_LOG(CPU, "targetAddr: %08x,js.compilerPC: %08x offset: %08x, op: %08x\n", targetAddr, js.compilerPC, offset, op);
-
 	// Take the branch
 	WriteExit(targetAddr, 0);
 
@@ -143,7 +142,6 @@ void Jit::BranchRSZeroComp(u32 op, PpcGen::FixupBranchType cc, bool andLink, boo
 	// Take the branch
 	if (andLink)
 	{
-		//Break();
 		MOVI2R(SREG, js.compilerPC + 8);
 		STW(SREG, CTXREG, MIPS_REG_RA * 4);
 	}
@@ -339,7 +337,6 @@ void Jit::Comp_Jump(u32 op) {
 		break;
 
 	case 3: //jal
-		//Break();
 		gpr.MapReg(MIPS_REG_RA, MAP_NOINIT | MAP_DIRTY);
 		MOVI2R(gpr.R(MIPS_REG_RA), js.compilerPC + 8);
 		CompileDelaySlot(DELAYSLOT_NICE);
@@ -393,7 +390,6 @@ void Jit::Comp_JumpReg(u32 op) {
 		break;
 	case 9: //jalr
 		// mips->reg = js.compilerPC + 8;
-		//Break();
 		MOVI2R(SREG, js.compilerPC + 8);
 		STW(SREG, CTXREG, MIPS_REG_RA * 4);
 		break;
diff --git a/Core/MIPS/PPC/PpcJit.cpp b/Core/MIPS/PPC/PpcJit.cpp
index 9e31b001a8..00893d46f7 100644
--- a/Core/MIPS/PPC/PpcJit.cpp
+++ b/Core/MIPS/PPC/PpcJit.cpp
@@ -31,6 +31,7 @@ void Jit::CompileDelaySlot(int flags)
 		// Save flags register
 		MOVI2R(SREG, (u32)&delaySlotFlagsValue);
 		STW(FLAGREG, SREG);
+		MFCR(R19);
 	}
 
 	js.inDelaySlot = true;
@@ -45,6 +46,7 @@ void Jit::CompileDelaySlot(int flags)
 		// Restore flags register
 		MOVI2R(SREG, (u32)&delaySlotFlagsValue);
 		LWZ(FLAGREG, SREG);
+		MTCR(R19);
 	}
 }
 
diff --git a/Core/MIPS/PPC/PpcRegCache.cpp b/Core/MIPS/PPC/PpcRegCache.cpp
index 04a4ebce7a..67bd5b5a02 100644
--- a/Core/MIPS/PPC/PpcRegCache.cpp
+++ b/Core/MIPS/PPC/PpcRegCache.cpp
@@ -50,7 +50,7 @@ const PPCReg *PpcRegCache::GetMIPSAllocationOrder(int &count) {
 	// R9 and upwards are reserved for jit basics.
 	if (options_->downcountInRegister) {
 		static const PPCReg allocationOrder[] = {
-			/*R14, R15, R16, R17, R18, */R19,
+			/*R14, R15, R16, R17, R18, R19,*/
 			R20, R21, R22, R23, R24, R25, 
 			R26, R27, R28, R29,	R30, R31,
 		};
@@ -58,7 +58,7 @@ const PPCReg *PpcRegCache::GetMIPSAllocationOrder(int &count) {
 		return allocationOrder;
 	} else {
 		static const PPCReg allocationOrder2[] = {
-			/*R14, R15, R16, R17, R18,*/ R19,
+			/*R14, R15, R16, R17, R18, R19,*/
 			R20, R21, R22, R23, R24, R25, 
 			R26, R27, R28, R29,	R30, R31,
 		};