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Mask out fcr31 bits that can't be set on a PSP.

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Unknown W. Brackets 2013-11-14 23:57:28 -08:00
parent 21c9577801
commit 5128083d93
2 changed files with 2 additions and 1 deletions
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1
Core/MIPS/ARM/ArmCompFPU.cpp
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@ -385,6 +385,7 @@ void Jit::Comp_mxc1(MIPSOpcode op)
VMSR(R1);
*/
// Update MIPS state
// TODO: Technically, should mask by 0x0181FFFF. Maybe just put all of FCR31 in the reg?
STR(gpr.R(rt), CTXREG, offsetof(MIPSState, fcr31));
#ifdef HAVE_ARMV7
UBFX(gpr.R(MIPS_REG_FPCOND), gpr.R(rt), 23, 1);

2
Core/MIPS/MIPS.cpp
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@ -206,7 +206,7 @@ void MIPSState::WriteFCR(int reg, int value)
{
if (reg == 31)
{
fcr31 = value;
fcr31 = value & 0x0181FFFF;
fpcond = (value >> 23) & 1;
}
else