From 5128083d934b91f548598efe5f139fa982b3d306 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Thu, 14 Nov 2013 23:57:28 -0800 Subject: [PATCH] Mask out fcr31 bits that can't be set on a PSP. --- Core/MIPS/ARM/ArmCompFPU.cpp | 1 + Core/MIPS/MIPS.cpp | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/Core/MIPS/ARM/ArmCompFPU.cpp b/Core/MIPS/ARM/ArmCompFPU.cpp index df7cf69013..19f11f2a37 100644 --- a/Core/MIPS/ARM/ArmCompFPU.cpp +++ b/Core/MIPS/ARM/ArmCompFPU.cpp @@ -385,6 +385,7 @@ void Jit::Comp_mxc1(MIPSOpcode op) VMSR(R1); */ // Update MIPS state + // TODO: Technically, should mask by 0x0181FFFF. Maybe just put all of FCR31 in the reg? STR(gpr.R(rt), CTXREG, offsetof(MIPSState, fcr31)); #ifdef HAVE_ARMV7 UBFX(gpr.R(MIPS_REG_FPCOND), gpr.R(rt), 23, 1); diff --git a/Core/MIPS/MIPS.cpp b/Core/MIPS/MIPS.cpp index 153a2f4155..edc8d4f5ba 100644 --- a/Core/MIPS/MIPS.cpp +++ b/Core/MIPS/MIPS.cpp @@ -206,7 +206,7 @@ void MIPSState::WriteFCR(int reg, int value) { if (reg == 31) { - fcr31 = value; + fcr31 = value & 0x0181FFFF; fpcond = (value >> 23) & 1; } else