mirror of
https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
jit few cleanup
This commit is contained in:
Ced2911
parent
5b87d222f4
commit
2cc17cbcc1
8 changed files with 75 additions and 172 deletions
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@ -1,10 +1,10 @@
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#include "Common/ChunkFile.h"
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#include "../../Core.h"
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#include "../../CoreTiming.h"
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#include "../MIPS.h"
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#include "../MIPSCodeUtils.h"
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#include "../MIPSInt.h"
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#include "../MIPSTables.h"
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#include "Core/Core.h"
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#include "Core/CoreTiming.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/MIPSInt.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "PpcRegCache.h"
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#include "ppcEmitter.h"
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@ -23,16 +23,11 @@ static void JitAt()
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namespace MIPSComp
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{
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//Jit * jit=NULL;
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static int dontLogBlocks = 20;
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static int logBlocks = 40;
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const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
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{
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NOTICE_LOG(CPU, "DoJit %08x - %08x\n", mips_->pc, mips_->downcount);
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js.cancel = false;
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js.blockStart = js.compilerPC = mips_->pc;
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js.downcountAmount = 0;
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@ -44,18 +39,12 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
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// We add a check before the block, used when entering from a linked block.
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b->checkedEntry = GetCodePtr();
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// Downcount flag check. The last block decremented downcounter, and the flag should still be available.
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//SetCC(CC_LT);
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MOVI2R(SREG, js.blockStart);
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//Break();
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// Cmp ??
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// if (currentMIPS->downcount<0)
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CMPI(DCNTREG, 0);
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BLT((const void *)outerLoopPCInR0);
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// if (currentMIPS->downcount<0)
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//BGT((const void *)outerLoopPCInR0);
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b->normalEntry = GetCodePtr();
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// TODO: this needs work
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@ -85,16 +74,6 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
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js.compilerPC += 4;
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numInstructions++;
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/*
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if (!cpu_info.bArmV7 && (GetCodePtr() - b->checkedEntry - partialFlushOffset) > 4020)
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{
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// We need to prematurely flush as we are out of range
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FixupBranch skip = B_CC(CC_AL);
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FlushLitPool();
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SetJumpTarget(skip);
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partialFlushOffset = GetCodePtr() - b->checkedEntry;
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}
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*/
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}
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//FlushLitPool();
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#ifdef LOGASM
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@ -113,11 +92,7 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
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INFO_LOG(DYNA_REC, "=============== ARM ===============");
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DisassembleArm(b->normalEntry, GetCodePtr() - b->normalEntry);
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}
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#endif
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//printf("DoJitend %08x - %08x - %08x\n", mips_->pc, mips_->downcount, js.compilerPC);
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#endif
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//DumpJit();
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AlignCode16();
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@ -130,11 +105,13 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
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}
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void Jit::DumpJit() {
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#ifdef _XBOX
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u32 len = (u32)GetCodePtr() - (u32)GetBasePtr();
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FILE * fd;
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fd = fopen("game:\\jit.bin", "wb");
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fwrite(GetBasePtr(), len, 1, fd);
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fclose(fd);
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#endif
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}
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void Jit::GenerateFixedCode() {
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@ -144,7 +121,6 @@ void Jit::GenerateFixedCode() {
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INFO_LOG(HLE, "enterCode: 0x%08p", enterCode);
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INFO_LOG(HLE, "GetBasePtr: 0x%08p", GetBasePtr());
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#if 1
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// Write Prologue (setup stack frame etc ...)
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// Save Lr
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MFLR(R12);
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@ -162,15 +138,11 @@ void Jit::GenerateFixedCode() {
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// allocate stack
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STWU(R1, R1, -stackFrameSize);
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#endif
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#if 1
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// Map fixed register
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MOVI2R(BASEREG, (u32)Memory::base);
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MOVI2R(CTXREG, (u32)mips_);
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MOVI2R(CODEREG, (u32)GetBasePtr());
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//Break();
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// Update downcount reg value from memory
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RestoreDowncount(DCNTREG);
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@ -205,18 +177,16 @@ void Jit::GenerateFixedCode() {
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// The result of slice decrementation should be in flags if somebody jumped here
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// IMPORTANT - We jump on negative, not carry!!!
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// branch to bailCoreState: (jump if(what ??) negative )
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//FixupBranch bailCoreState = B_CC(CC_MI); // BLT ???
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FixupBranch bailCoreState = BLT(); // BLT ???
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// SREG = coreState
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MOVI2R(SREG, (u32)&coreState);
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// ??? Compare coreState and CORE_RUNNING
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// Compare coreState and CORE_RUNNING
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LWZ(SREG, SREG); // SREG = *SREG
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CMPI(SREG, 0); // compare 0(CORE_RUNNING) and CR0
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// branch to badCoreState: (jump if coreState != CORE_RUNNING)
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FixupBranch badCoreState = BNE(); // B_CC(CC_NEQ)
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FixupBranch badCoreState = BNE();
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// branch to skipToRealDispatch2:
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FixupBranch skipToRealDispatch2 = B(); //skip the sync and compare first time
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@ -303,28 +273,12 @@ void Jit::GenerateFixedCode() {
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// label bailCoreState:
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SetJumpTarget(bailCoreState);
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#if 0
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// Compare coreState and CORE_RUNNING
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MOVI2R(SREG, (u32)&coreState);
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LWZ(SREG, SREG); // SREG = *SREG => SREG = coreState
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CMPLI(SREG, 0); // compare 0(CORE_RUNNING) and corestate
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// if (coreState == CORE_RUNNING) check for downcount
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FixupBranch badcpustates = BNE();
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//BEQ(outerLoop);
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CMPI(DCNTREG, 0);
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BLE(outerLoop);
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SetJumpTarget(badcpustates);
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#else
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// Compare coreState and CORE_RUNNING
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MOVI2R(SREG, (u32)&coreState);
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LWZ(SREG, SREG); // SREG = *SREG => SREG = coreState
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CMPLI(SREG, 0); // compare 0(CORE_RUNNING) and corestate
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BEQ(outerLoop);
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#endif
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// }
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// badCoreState label:
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@ -336,9 +290,6 @@ void Jit::GenerateFixedCode() {
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// mips->downcount = DCNTREG
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SaveDowncount(DCNTREG);
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#endif
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#if 1
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// Write Epilogue (restore stack frame, return)
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// free stack
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ADDI(R1, R1, stackFrameSize);
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@ -353,11 +304,9 @@ void Jit::GenerateFixedCode() {
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// Restore Lr
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MTLR(R12);
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//Break();
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// Go back to caller
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BLR();
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#endif
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// Don't forget to zap the instruction cache!
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FlushIcache();
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@ -1,10 +1,10 @@
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#include "Common/ChunkFile.h"
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#include "../../Core.h"
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#include "../../CoreTiming.h"
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#include "../MIPS.h"
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#include "../MIPSCodeUtils.h"
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#include "../MIPSInt.h"
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#include "../MIPSTables.h"
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#include "Core/Core.h"
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#include "Core/CoreTiming.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/MIPSInt.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "PpcRegCache.h"
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#include "ppcEmitter.h"
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#include "Common/ChunkFile.h"
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#include "../../Core.h"
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#include "../../CoreTiming.h"
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#include "../MIPS.h"
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#include "../MIPSCodeUtils.h"
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#include "../MIPSInt.h"
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#include "../MIPSTables.h"
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#include "Core/Core.h"
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#include "Core/CoreTiming.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/MIPSInt.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "Core/Reporting.h"
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#include "Core/HLE/HLE.h"
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@ -59,39 +59,21 @@ void Jit::BranchRSRTComp(u32 op, PpcGen::FixupBranchType cc, bool likely)
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if (!likely && delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_NICE);
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if (cc == _BEQ || cc == _BNE) {
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if (gpr.IsImm(rt) && gpr.GetImm(rt) == 0)
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{
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gpr.MapReg(rs);
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CMPLI(gpr.R(rs), 0);
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}
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else if (gpr.IsImm(rs) && gpr.GetImm(rs) == 0) // only these are easily 'flippable'
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{
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gpr.MapReg(rt);
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CMPLI(gpr.R(rt), 0);
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}
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else
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{
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gpr.MapInIn(rs, rt);
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CMPL(gpr.R(rs), gpr.R(rt));
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}
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} else {
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if (gpr.IsImm(rt) && gpr.GetImm(rt) == 0)
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{
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gpr.MapReg(rs);
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CMPLI(gpr.R(rs), 0);
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}
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else
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{
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gpr.MapInIn(rs, rt);
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CMPL(gpr.R(rs), gpr.R(rt));
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}
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if (gpr.IsImm(rt) && gpr.GetImm(rt) == 0)
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{
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gpr.MapReg(rs);
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CMPLI(gpr.R(rs), 0);
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}
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else if (gpr.IsImm(rs) && gpr.GetImm(rs) == 0) // only these are easily 'flippable'
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{
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gpr.MapReg(rt);
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CMPLI(gpr.R(rt), 0);
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}
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else
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{
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gpr.MapInIn(rs, rt);
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CMPL(gpr.R(rs), gpr.R(rt));
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}
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//if (js.compilerPC == 0x089001c4) {
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// Break();
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// Break();
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//}
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PpcGen::FixupBranch ptr;
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if (!likely)
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@ -114,7 +96,6 @@ void Jit::BranchRSRTComp(u32 op, PpcGen::FixupBranchType cc, bool likely)
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// Take the branch
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WriteExit(targetAddr, 0);
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// !cond
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SetJumpTarget(ptr);
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// Not taken
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@ -170,6 +151,7 @@ void Jit::BranchRSZeroComp(u32 op, PpcGen::FixupBranchType cc, bool andLink, boo
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WriteExit(targetAddr, 0);
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SetJumpTarget(ptr);
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// Not taken
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WriteExit(js.compilerPC + 8, 1);
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@ -235,20 +217,11 @@ void Jit::BranchFPFlag(u32 op, PpcGen::FixupBranchType cc, bool likely)
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CompileDelaySlot(DELAYSLOT_NICE);
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FlushAll();
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//DebugBreak(); // not made !
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/*
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LWZ(SREG, CTXREG, offsetof(MIPSState, fpcond));
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//TST(SREG, Operand2(1, TYPE_IMM));
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*/
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LWZ(SREG, CTXREG, offsetof(MIPSState, fpcond));
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// should change CR0
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// change CR0
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ANDI(SREG, SREG, 1);
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PpcGen::FixupBranch ptr;
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if (!likely)
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{
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@ -307,14 +280,10 @@ void Jit::BranchVFPUFlag(u32 op, PpcGen::FixupBranchType cc, bool likely)
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int imm3 = (op >> 18) & 7;
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/*
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MOVI2R(R0, (u32)&(mips_->vfpuCtrl[VFPU_CTRL_CC]));
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LWZ(R0, R0, Operand2(0, TYPE_IMM));
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TST(R0, Operand2(1 << imm3, TYPE_IMM));
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*/
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MOVI2R(SREG, (u32)&(mips_->vfpuCtrl[VFPU_CTRL_CC]));
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LWZ(SREG, SREG, 0);
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// should change CR0
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// change CR0
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ANDI(SREG, SREG, 1 << imm3);
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PpcGen::FixupBranch ptr;
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@ -360,11 +329,7 @@ void Jit::Comp_Jump(u32 op) {
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}
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u32 off = ((op & 0x03FFFFFF) << 2);
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u32 targetAddr = (js.compilerPC & 0xF0000000) | off;
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/*if (op == 0x0a240070) {
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Break();
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}*/
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switch (op >> 26)
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{
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case 2: //j
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@ -1,10 +1,10 @@
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#include "Common/ChunkFile.h"
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#include "../../Core.h"
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#include "../../CoreTiming.h"
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#include "../MIPS.h"
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#include "../MIPSCodeUtils.h"
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#include "../MIPSInt.h"
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#include "../MIPSTables.h"
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#include "Core/Core.h"
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#include "Core/CoreTiming.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/MIPSInt.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "PpcRegCache.h"
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#include "ppcEmitter.h"
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@ -1,10 +1,10 @@
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#include "Common/ChunkFile.h"
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#include "../../Core.h"
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#include "../../CoreTiming.h"
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#include "../MIPS.h"
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#include "../MIPSCodeUtils.h"
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#include "../MIPSInt.h"
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#include "../MIPSTables.h"
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#include "Core/Core.h"
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#include "Core/CoreTiming.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/MIPSInt.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "PpcRegCache.h"
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#include "ppcEmitter.h"
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@ -1,10 +1,10 @@
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#include "Common/ChunkFile.h"
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#include "../../Core.h"
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#include "../../CoreTiming.h"
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#include "../MIPS.h"
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#include "../MIPSCodeUtils.h"
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#include "../MIPSInt.h"
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#include "../MIPSTables.h"
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#include "Core/Core.h"
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#include "Core/CoreTiming.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/MIPSInt.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "PpcRegCache.h"
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#include "ppcEmitter.h"
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@ -1,10 +1,10 @@
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#include "Common/ChunkFile.h"
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#include "../../Core.h"
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#include "../../CoreTiming.h"
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#include "../MIPS.h"
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#include "../MIPSCodeUtils.h"
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#include "../MIPSInt.h"
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#include "../MIPSTables.h"
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#include "Core/Core.h"
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#include "Core/CoreTiming.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/MIPSInt.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "PpcRegCache.h"
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#include "ppcEmitter.h"
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@ -21,7 +21,6 @@ namespace MIPSComp
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static u32 delaySlotFlagsValue;
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/** we use a flag non volatile flag (FLAGREG)r18, no need to save it **/
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void Jit::CompileDelaySlot(int flags)
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{
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// preserve flag around the delay slot! Maybe this is not always necessary on ARM where
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@ -29,7 +28,6 @@ void Jit::CompileDelaySlot(int flags)
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// delay slot, we're screwed.
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if (flags & DELAYSLOT_SAFE) {
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// Save flags register
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//Break();
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MOVI2R(SREG, (u32)&delaySlotFlagsValue);
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STW(FLAGREG, SREG);
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}
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@ -44,7 +42,6 @@ void Jit::CompileDelaySlot(int flags)
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if (flags & DELAYSLOT_SAFE) {
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// Restore flags register
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//Break();
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MOVI2R(SREG, (u32)&delaySlotFlagsValue);
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LWZ(FLAGREG, SREG);
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}
|
||||
|
|
@ -93,7 +90,7 @@ void Jit::RestoreDowncount(PPCReg r) {
|
|||
static void ShowDownCount() {
|
||||
if (currentMIPS->downcount<0) {
|
||||
//ERROR_LOG(DYNA_REC, "MIPSState, downcount %08x", currentMIPS->downcount);
|
||||
DebugBreak();
|
||||
Crash();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -127,18 +124,14 @@ void Jit::Comp_Generic(u32 op) {
|
|||
// Save mips PC and cycles
|
||||
SaveDowncount(DCNTREG);
|
||||
|
||||
//// Set func param
|
||||
//if (op == 0x00009021)
|
||||
// Break();
|
||||
|
||||
// call interpreted function
|
||||
MOVI2R(R3, op);
|
||||
|
||||
QuickCallFunction((void *)func);
|
||||
|
||||
// restore pc and cycles
|
||||
RestoreDowncount(DCNTREG);
|
||||
}
|
||||
// Might have eaten prefixes, hard to tell...
|
||||
// Might have eaten prefixes, hard to tell...
|
||||
if ((MIPSGetInfo(op) & IS_VFPU) != 0)
|
||||
js.PrefixStart();
|
||||
}
|
||||
|
|
@ -188,13 +181,13 @@ Jit::Jit(MIPSState *mips) : blocks(mips, this), gpr(mips, &jo),mips_(mips)
|
|||
js.startDefaultPrefix = true;
|
||||
}
|
||||
|
||||
void Jit::RunLoopUntil(u64 globalticks) {
|
||||
// Run the compiled code
|
||||
|
||||
INFO_LOG(HLE, "enterCode: %08p", enterCode);
|
||||
|
||||
void Jit::RunLoopUntil(u64 globalticks) {
|
||||
#ifdef _XBOX
|
||||
// force stack alinement
|
||||
_alloca(8*1024);
|
||||
#endif
|
||||
|
||||
// Run the compiled code
|
||||
((void (*)())enterCode)();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -19,10 +19,6 @@
|
|||
#include "PpcRegCache.h"
|
||||
#include "PpcJit.h"
|
||||
|
||||
#if defined(MAEMO)
|
||||
#include "stddef.h"
|
||||
#endif
|
||||
|
||||
using namespace PpcGen;
|
||||
|
||||
PpcRegCache::PpcRegCache(MIPSState *mips, MIPSComp::PpcJitOptions *options) : mips_(mips), options_(options) {
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue