diff --git a/Core/MIPS/PPC/PpcAsm.cpp b/Core/MIPS/PPC/PpcAsm.cpp
index bef21cc4e6..3acf74af50 100644
--- a/Core/MIPS/PPC/PpcAsm.cpp
+++ b/Core/MIPS/PPC/PpcAsm.cpp
@@ -1,10 +1,10 @@
 #include "Common/ChunkFile.h"
-#include "../../Core.h"
-#include "../../CoreTiming.h"
-#include "../MIPS.h"
-#include "../MIPSCodeUtils.h"
-#include "../MIPSInt.h"
-#include "../MIPSTables.h"
+#include "Core/Core.h"
+#include "Core/CoreTiming.h"
+#include "Core/MIPS/MIPS.h"
+#include "Core/MIPS/MIPSCodeUtils.h"
+#include "Core/MIPS/MIPSInt.h"
+#include "Core/MIPS/MIPSTables.h"
 
 #include "PpcRegCache.h"
 #include "ppcEmitter.h"
@@ -23,16 +23,11 @@ static void JitAt()
 
 namespace MIPSComp
 {
-	//Jit * jit=NULL;
-
 static int dontLogBlocks = 20;
 static int logBlocks = 40;
 
 const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
 {
-	NOTICE_LOG(CPU, "DoJit %08x - %08x\n", mips_->pc, mips_->downcount);
-
-
 	js.cancel = false;
 	js.blockStart = js.compilerPC = mips_->pc;
 	js.downcountAmount = 0;
@@ -44,18 +39,12 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
 	// We add a check before the block, used when entering from a linked block.
 	b->checkedEntry = GetCodePtr();
 	// Downcount flag check. The last block decremented downcounter, and the flag should still be available.
-	//SetCC(CC_LT);
-
 	
 	MOVI2R(SREG, js.blockStart);
 
-	//Break();
-
-	// Cmp ??
+	// if (currentMIPS->downcount<0)
 	CMPI(DCNTREG, 0);
 	BLT((const void *)outerLoopPCInR0);
-	// if (currentMIPS->downcount<0)
-	//BGT((const void *)outerLoopPCInR0);
 
 	b->normalEntry = GetCodePtr();
 	// TODO: this needs work
@@ -85,16 +74,6 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
 	
 		js.compilerPC += 4;
 		numInstructions++;
-		/*
-		if (!cpu_info.bArmV7 && (GetCodePtr() - b->checkedEntry - partialFlushOffset) > 4020)
-		{
-			// We need to prematurely flush as we are out of range
-			FixupBranch skip = B_CC(CC_AL);
-			FlushLitPool();
-			SetJumpTarget(skip);
-			partialFlushOffset = GetCodePtr() - b->checkedEntry;
-		}
-		*/
 	}
 	//FlushLitPool();
 #ifdef LOGASM
@@ -113,11 +92,7 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
 		INFO_LOG(DYNA_REC, "=============== ARM ===============");
 		DisassembleArm(b->normalEntry, GetCodePtr() - b->normalEntry);
 	}
-#endif
-
-	
-	//printf("DoJitend %08x - %08x - %08x\n", mips_->pc, mips_->downcount, js.compilerPC);
-	
+#endif	
 	//DumpJit();
 
 	AlignCode16();
@@ -130,11 +105,13 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
 }
 
 void Jit::DumpJit() {
+#ifdef _XBOX
 	u32 len = (u32)GetCodePtr() - (u32)GetBasePtr();
 	FILE * fd;
 	fd = fopen("game:\\jit.bin", "wb");
 	fwrite(GetBasePtr(), len, 1, fd);
 	fclose(fd);
+#endif
 }
 
 void Jit::GenerateFixedCode() {
@@ -144,7 +121,6 @@ void Jit::GenerateFixedCode() {
 	INFO_LOG(HLE, "enterCode: 0x%08p", enterCode);	
 	INFO_LOG(HLE, "GetBasePtr: 0x%08p", GetBasePtr());
 
-#if 1
 	// Write Prologue (setup stack frame etc ...)
 	// Save Lr
 	MFLR(R12);
@@ -162,15 +138,11 @@ void Jit::GenerateFixedCode() {
 
 	// allocate stack
 	STWU(R1, R1, -stackFrameSize);
-#endif
-
-#if 1
 	
 	// Map fixed register
 	MOVI2R(BASEREG,	(u32)Memory::base);
 	MOVI2R(CTXREG,	(u32)mips_);
 	MOVI2R(CODEREG, (u32)GetBasePtr());
-	//Break();
 
 	// Update downcount reg value from memory
 	RestoreDowncount(DCNTREG);
@@ -205,18 +177,16 @@ void Jit::GenerateFixedCode() {
 		// The result of slice decrementation should be in flags if somebody jumped here
 		// IMPORTANT - We jump on negative, not carry!!!
 		// branch to bailCoreState: (jump if(what ??) negative )
-		//FixupBranch bailCoreState = B_CC(CC_MI); // BLT ???
-
 		FixupBranch bailCoreState = BLT(); // BLT ???
 
 		// SREG = coreState
 		MOVI2R(SREG, (u32)&coreState);
-		// ??? Compare coreState and CORE_RUNNING
+		// Compare coreState and CORE_RUNNING
 		LWZ(SREG, SREG); // SREG = *SREG
 		CMPI(SREG, 0); // compare 0(CORE_RUNNING) and CR0
 
 		// branch to badCoreState: (jump if coreState != CORE_RUNNING)
-		FixupBranch badCoreState = BNE(); // B_CC(CC_NEQ)
+		FixupBranch badCoreState = BNE(); 
 
 		// branch to skipToRealDispatch2:
 		FixupBranch skipToRealDispatch2 = B(); //skip the sync and compare first time
@@ -303,28 +273,12 @@ void Jit::GenerateFixedCode() {
 		// label bailCoreState:
 		SetJumpTarget(bailCoreState);
 
-#if 0
-		// Compare coreState and CORE_RUNNING
-		MOVI2R(SREG, (u32)&coreState);
-		LWZ(SREG, SREG); // SREG = *SREG => SREG = coreState
-		CMPLI(SREG, 0); // compare 0(CORE_RUNNING) and corestate
-				
-		// if (coreState == CORE_RUNNING) check for downcount
-		FixupBranch badcpustates = BNE();
-		
-		//BEQ(outerLoop);
-		CMPI(DCNTREG, 0);
-		BLE(outerLoop);
-		
-		SetJumpTarget(badcpustates);
-#else
 		// Compare coreState and CORE_RUNNING
 		MOVI2R(SREG, (u32)&coreState);
 		LWZ(SREG, SREG); // SREG = *SREG => SREG = coreState
 		CMPLI(SREG, 0); // compare 0(CORE_RUNNING) and corestate
 
 		BEQ(outerLoop);
-#endif
 	// }
 
 	// badCoreState label:
@@ -336,9 +290,6 @@ void Jit::GenerateFixedCode() {
 	// mips->downcount = DCNTREG
 	SaveDowncount(DCNTREG);
 
-#endif
-
-#if 1
 	// Write Epilogue (restore stack frame, return)
 	// free stack
 	ADDI(R1, R1, stackFrameSize);	
@@ -353,11 +304,9 @@ void Jit::GenerateFixedCode() {
 
 	// Restore Lr
 	MTLR(R12);
-	//Break();
 
 	// Go back to caller
 	BLR();
-#endif
 
 	// Don't forget to zap the instruction cache!
 	FlushIcache();
diff --git a/Core/MIPS/PPC/PpcCompAlu.cpp b/Core/MIPS/PPC/PpcCompAlu.cpp
index c470b3d351..10fd3c84a4 100644
--- a/Core/MIPS/PPC/PpcCompAlu.cpp
+++ b/Core/MIPS/PPC/PpcCompAlu.cpp
@@ -1,10 +1,10 @@
 #include "Common/ChunkFile.h"
-#include "../../Core.h"
-#include "../../CoreTiming.h"
-#include "../MIPS.h"
-#include "../MIPSCodeUtils.h"
-#include "../MIPSInt.h"
-#include "../MIPSTables.h"
+#include "Core/Core.h"
+#include "Core/CoreTiming.h"
+#include "Core/MIPS/MIPS.h"
+#include "Core/MIPS/MIPSCodeUtils.h"
+#include "Core/MIPS/MIPSInt.h"
+#include "Core/MIPS/MIPSTables.h"
 
 #include "PpcRegCache.h"
 #include "ppcEmitter.h"
diff --git a/Core/MIPS/PPC/PpcCompBranch.cpp b/Core/MIPS/PPC/PpcCompBranch.cpp
index 6e7f3ea7f5..10b959a098 100644
--- a/Core/MIPS/PPC/PpcCompBranch.cpp
+++ b/Core/MIPS/PPC/PpcCompBranch.cpp
@@ -1,10 +1,10 @@
 #include "Common/ChunkFile.h"
-#include "../../Core.h"
-#include "../../CoreTiming.h"
-#include "../MIPS.h"
-#include "../MIPSCodeUtils.h"
-#include "../MIPSInt.h"
-#include "../MIPSTables.h"
+#include "Core/Core.h"
+#include "Core/CoreTiming.h"
+#include "Core/MIPS/MIPS.h"
+#include "Core/MIPS/MIPSCodeUtils.h"
+#include "Core/MIPS/MIPSInt.h"
+#include "Core/MIPS/MIPSTables.h"
 
 #include "Core/Reporting.h"
 #include "Core/HLE/HLE.h"
@@ -59,39 +59,21 @@ void Jit::BranchRSRTComp(u32 op, PpcGen::FixupBranchType cc, bool likely)
 	if (!likely && delaySlotIsNice)
 		CompileDelaySlot(DELAYSLOT_NICE);
 
-	if (cc == _BEQ || cc == _BNE) {
-		if (gpr.IsImm(rt) && gpr.GetImm(rt) == 0)
-		{
-			gpr.MapReg(rs);
-			CMPLI(gpr.R(rs), 0);
-		}
-		else if (gpr.IsImm(rs) && gpr.GetImm(rs) == 0)  // only these are easily 'flippable'
-		{
-			gpr.MapReg(rt);
-			CMPLI(gpr.R(rt), 0);
-		}
-		else 
-		{
-			gpr.MapInIn(rs, rt);
-			CMPL(gpr.R(rs), gpr.R(rt));
-		}
-	} else {	
-		if (gpr.IsImm(rt) && gpr.GetImm(rt) == 0)
-		{
-			gpr.MapReg(rs);
-			CMPLI(gpr.R(rs), 0);
-		}
-		else 
-		{
-			gpr.MapInIn(rs, rt);
-			CMPL(gpr.R(rs), gpr.R(rt));
-		}
+	if (gpr.IsImm(rt) && gpr.GetImm(rt) == 0)
+	{
+		gpr.MapReg(rs);
+		CMPLI(gpr.R(rs), 0);
+	}
+	else if (gpr.IsImm(rs) && gpr.GetImm(rs) == 0)  // only these are easily 'flippable'
+	{
+		gpr.MapReg(rt);
+		CMPLI(gpr.R(rt), 0);
+	}
+	else 
+	{
+		gpr.MapInIn(rs, rt);
+		CMPL(gpr.R(rs), gpr.R(rt));
 	}
-	
-	//if (js.compilerPC == 0x089001c4) {
-	//	Break();
-	//	Break();
-	//}
 
 	PpcGen::FixupBranch ptr;
 	if (!likely)
@@ -114,7 +96,6 @@ void Jit::BranchRSRTComp(u32 op, PpcGen::FixupBranchType cc, bool likely)
 	// Take the branch
 	WriteExit(targetAddr, 0);
 
-	// !cond 
 	SetJumpTarget(ptr);
 
 	// Not taken
@@ -170,6 +151,7 @@ void Jit::BranchRSZeroComp(u32 op, PpcGen::FixupBranchType cc, bool andLink, boo
 	WriteExit(targetAddr, 0);
 
 	SetJumpTarget(ptr);
+
 	// Not taken
 	WriteExit(js.compilerPC + 8, 1);
 
@@ -235,20 +217,11 @@ void Jit::BranchFPFlag(u32 op, PpcGen::FixupBranchType cc, bool likely)
 		CompileDelaySlot(DELAYSLOT_NICE);
 
 	FlushAll();
-
 	
-	//DebugBreak(); // not made !
-
-	/*
 	LWZ(SREG, CTXREG, offsetof(MIPSState, fpcond));
-	//TST(SREG, Operand2(1, TYPE_IMM)); 
-	*/
-
-	LWZ(SREG, CTXREG, offsetof(MIPSState, fpcond));
-	// should change CR0
+	// change CR0
 	ANDI(SREG, SREG, 1);
 
-
 	PpcGen::FixupBranch ptr;
 	if (!likely)
 	{
@@ -307,14 +280,10 @@ void Jit::BranchVFPUFlag(u32 op, PpcGen::FixupBranchType cc, bool likely)
 
 	int imm3 = (op >> 18) & 7;
 
-	/*
-	MOVI2R(R0, (u32)&(mips_->vfpuCtrl[VFPU_CTRL_CC]));
-	LWZ(R0, R0, Operand2(0, TYPE_IMM));
-	TST(R0, Operand2(1 << imm3, TYPE_IMM));
-	*/
+
 	MOVI2R(SREG,  (u32)&(mips_->vfpuCtrl[VFPU_CTRL_CC]));
 	LWZ(SREG, SREG, 0);
-	// should change CR0
+	// change CR0
 	ANDI(SREG, SREG, 1 << imm3);
 
 	PpcGen::FixupBranch ptr;
@@ -360,11 +329,7 @@ void Jit::Comp_Jump(u32 op) {
 	}
 	u32 off = ((op & 0x03FFFFFF) << 2);
 	u32 targetAddr = (js.compilerPC & 0xF0000000) | off;
-
-	/*if (op == 0x0a240070) {
-		Break();
-	}*/
-
+	
 	switch (op >> 26) 
 	{
 	case 2: //j
diff --git a/Core/MIPS/PPC/PpcCompFpu.cpp b/Core/MIPS/PPC/PpcCompFpu.cpp
index f4604e0b62..c0e9b320d4 100644
--- a/Core/MIPS/PPC/PpcCompFpu.cpp
+++ b/Core/MIPS/PPC/PpcCompFpu.cpp
@@ -1,10 +1,10 @@
 #include "Common/ChunkFile.h"
-#include "../../Core.h"
-#include "../../CoreTiming.h"
-#include "../MIPS.h"
-#include "../MIPSCodeUtils.h"
-#include "../MIPSInt.h"
-#include "../MIPSTables.h"
+#include "Core/Core.h"
+#include "Core/CoreTiming.h"
+#include "Core/MIPS/MIPS.h"
+#include "Core/MIPS/MIPSCodeUtils.h"
+#include "Core/MIPS/MIPSInt.h"
+#include "Core/MIPS/MIPSTables.h"
 
 #include "PpcRegCache.h"
 #include "ppcEmitter.h"
diff --git a/Core/MIPS/PPC/PpcCompLoadStore.cpp b/Core/MIPS/PPC/PpcCompLoadStore.cpp
index f1074bd3a9..e213c3078f 100644
--- a/Core/MIPS/PPC/PpcCompLoadStore.cpp
+++ b/Core/MIPS/PPC/PpcCompLoadStore.cpp
@@ -1,10 +1,10 @@
 #include "Common/ChunkFile.h"
-#include "../../Core.h"
-#include "../../CoreTiming.h"
-#include "../MIPS.h"
-#include "../MIPSCodeUtils.h"
-#include "../MIPSInt.h"
-#include "../MIPSTables.h"
+#include "Core/Core.h"
+#include "Core/CoreTiming.h"
+#include "Core/MIPS/MIPS.h"
+#include "Core/MIPS/MIPSCodeUtils.h"
+#include "Core/MIPS/MIPSInt.h"
+#include "Core/MIPS/MIPSTables.h"
 
 #include "PpcRegCache.h"
 #include "ppcEmitter.h"
diff --git a/Core/MIPS/PPC/PpcCompVFPU.cpp b/Core/MIPS/PPC/PpcCompVFPU.cpp
index ba3c2acfeb..70973be151 100644
--- a/Core/MIPS/PPC/PpcCompVFPU.cpp
+++ b/Core/MIPS/PPC/PpcCompVFPU.cpp
@@ -1,10 +1,10 @@
 #include "Common/ChunkFile.h"
-#include "../../Core.h"
-#include "../../CoreTiming.h"
-#include "../MIPS.h"
-#include "../MIPSCodeUtils.h"
-#include "../MIPSInt.h"
-#include "../MIPSTables.h"
+#include "Core/Core.h"
+#include "Core/CoreTiming.h"
+#include "Core/MIPS/MIPS.h"
+#include "Core/MIPS/MIPSCodeUtils.h"
+#include "Core/MIPS/MIPSInt.h"
+#include "Core/MIPS/MIPSTables.h"
 
 #include "PpcRegCache.h"
 #include "ppcEmitter.h"
diff --git a/Core/MIPS/PPC/PpcJit.cpp b/Core/MIPS/PPC/PpcJit.cpp
index a3e267f9de..24b1443e6d 100644
--- a/Core/MIPS/PPC/PpcJit.cpp
+++ b/Core/MIPS/PPC/PpcJit.cpp
@@ -1,10 +1,10 @@
 #include "Common/ChunkFile.h"
-#include "../../Core.h"
-#include "../../CoreTiming.h"
-#include "../MIPS.h"
-#include "../MIPSCodeUtils.h"
-#include "../MIPSInt.h"
-#include "../MIPSTables.h"
+#include "Core/Core.h"
+#include "Core/CoreTiming.h"
+#include "Core/MIPS/MIPS.h"
+#include "Core/MIPS/MIPSCodeUtils.h"
+#include "Core/MIPS/MIPSInt.h"
+#include "Core/MIPS/MIPSTables.h"
 
 #include "PpcRegCache.h"
 #include "ppcEmitter.h"
@@ -21,7 +21,6 @@ namespace MIPSComp
 
 static u32 delaySlotFlagsValue;
 
-/** we use a flag non volatile flag (FLAGREG)r18, no need to save it **/
 void Jit::CompileDelaySlot(int flags)
 {
 	// preserve flag around the delay slot! Maybe this is not always necessary on ARM where 
@@ -29,7 +28,6 @@ void Jit::CompileDelaySlot(int flags)
 	// delay slot, we're screwed.
 	if (flags & DELAYSLOT_SAFE) {
 		// Save flags register
-		//Break();
 		MOVI2R(SREG, (u32)&delaySlotFlagsValue);
 		STW(FLAGREG, SREG);
 	}
@@ -44,7 +42,6 @@ void Jit::CompileDelaySlot(int flags)
 
 	if (flags & DELAYSLOT_SAFE) {
 		// Restore flags register
-		//Break();
 		MOVI2R(SREG, (u32)&delaySlotFlagsValue);
 		LWZ(FLAGREG, SREG);
 	}
@@ -93,7 +90,7 @@ void Jit::RestoreDowncount(PPCReg r) {
 static void ShowDownCount() {
 	if (currentMIPS->downcount<0) {
 		//ERROR_LOG(DYNA_REC, "MIPSState, downcount %08x", currentMIPS->downcount);
-		DebugBreak();
+		Crash();
 	}
 }
 
@@ -127,18 +124,14 @@ void Jit::Comp_Generic(u32 op) {
 		// Save mips PC and cycles
 		SaveDowncount(DCNTREG);
 
-		//// Set func param
-		//if (op == 0x00009021) 
-		//	Break();
-
+		// call interpreted function
 		MOVI2R(R3, op);
-
 		QuickCallFunction((void *)func);
 
 		// restore pc and cycles
 		RestoreDowncount(DCNTREG);
 	}
-		// Might have eaten prefixes, hard to tell...
+	// Might have eaten prefixes, hard to tell...
 	if ((MIPSGetInfo(op) & IS_VFPU) != 0)
 		js.PrefixStart();
 }
@@ -188,13 +181,13 @@ Jit::Jit(MIPSState *mips) : blocks(mips, this), gpr(mips, &jo),mips_(mips)
 	js.startDefaultPrefix = true;
 }
 
-void Jit::RunLoopUntil(u64 globalticks) {
-	// Run the compiled code
-	
-	INFO_LOG(HLE, "enterCode: %08p", enterCode);
-	
+void Jit::RunLoopUntil(u64 globalticks) {	
+#ifdef _XBOX
+	// force stack alinement
 	_alloca(8*1024);
+#endif
 	
+	// Run the compiled code
 	((void (*)())enterCode)();
 }
 
diff --git a/Core/MIPS/PPC/PpcRegCache.cpp b/Core/MIPS/PPC/PpcRegCache.cpp
index 98bd2521d6..31ae0778be 100644
--- a/Core/MIPS/PPC/PpcRegCache.cpp
+++ b/Core/MIPS/PPC/PpcRegCache.cpp
@@ -19,10 +19,6 @@
 #include "PpcRegCache.h"
 #include "PpcJit.h"
 
-#if defined(MAEMO)
-#include "stddef.h"
-#endif
-
 using namespace PpcGen;
 
 PpcRegCache::PpcRegCache(MIPSState *mips, MIPSComp::PpcJitOptions *options) : mips_(mips), options_(options) {