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Fix/workaround ARM64 with the MASKED_PSP_MEMORY build flag.

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This commit is contained in:
Henrik Rydgård 2020-11-03 00:13:52 +01:00
parent dd7983c8dd
commit 1b596ef82b
4 changed files with 8 additions and 1 deletions
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1
Core/MIPS/ARM64/Arm64Asm.cpp
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@ -16,6 +16,7 @@
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include "ppsspp_config.h"
#if PPSSPP_ARCH(ARM64)
#include "Common/Log.h"

3
Core/MIPS/ARM64/Arm64CompLoadStore.cpp
View file

@ -311,6 +311,7 @@ namespace MIPSComp {
case 40: //sb
case 41: //sh
case 43: //sw
#ifndef MASKED_PSP_MEMORY
if (jo.cachePointers && g_Config.bFastMemory) {
// ARM has smaller load/store immediate displacements than MIPS, 12 bits - and some memory ops only have 8 bits.
int offsetRange = 0x3ff;
@ -327,6 +328,7 @@ namespace MIPSComp {
gpr.MapReg(rt, load ? MAP_NOINIT : 0);
targetReg = gpr.R(rt);
}
switch (o) {
case 35: LDR(INDEX_UNSIGNED, targetReg, gpr.RPtr(rs), offset); break;
case 37: LDRH(INDEX_UNSIGNED, targetReg, gpr.RPtr(rs), offset); break;
@ -342,6 +344,7 @@ namespace MIPSComp {
break;
}
}
#endif
if (!load && gpr.IsImm(rt) && gpr.TryMapTempImm(rt) != INVALID_REG) {
// We're storing an immediate value, let's see if we can optimize rt.

1
Core/MIPS/ARM64/Arm64CompVFPU.cpp
View file

@ -358,7 +358,6 @@ namespace MIPSComp {
ADD(SCRATCH1_64, SCRATCH1_64, MEMBASEREG);
}
}
fp.STP(32, INDEX_SIGNED, fpr.V(vregs[0]), fpr.V(vregs[1]), SCRATCH1_64, 0);
fp.STP(32, INDEX_SIGNED, fpr.V(vregs[2]), fpr.V(vregs[3]), SCRATCH1_64, 8);

4
Core/MIPS/ARM64/Arm64Jit.cpp
View file

@ -100,6 +100,10 @@ Arm64Jit::Arm64Jit(MIPSState *mips) : blocks(mips, this), gpr(mips, &js, &jo), f
jo.enablePointerify = false;
}
#ifdef MASKED_PSP_MEMORY
jo.enablePointerify = false;
#endif
logBlocks = 0;
dontLogBlocks = 0;
blocks.Init();