From 1b596ef82bceff977a333a50d2b55087e1d490d0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Henrik=20Rydg=C3=A5rd?= <hrydgard@gmail.com>
Date: Tue, 3 Nov 2020 00:13:52 +0100
Subject: [PATCH] Fix/workaround ARM64 with the MASKED_PSP_MEMORY build flag.

---
 Core/MIPS/ARM64/Arm64Asm.cpp           | 1 +
 Core/MIPS/ARM64/Arm64CompLoadStore.cpp | 3 +++
 Core/MIPS/ARM64/Arm64CompVFPU.cpp      | 1 -
 Core/MIPS/ARM64/Arm64Jit.cpp           | 4 ++++
 4 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/Core/MIPS/ARM64/Arm64Asm.cpp b/Core/MIPS/ARM64/Arm64Asm.cpp
index 99f4dadf65..b95b8e54b4 100644
--- a/Core/MIPS/ARM64/Arm64Asm.cpp
+++ b/Core/MIPS/ARM64/Arm64Asm.cpp
@@ -16,6 +16,7 @@
 // https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
 
 #include "ppsspp_config.h"
+
 #if PPSSPP_ARCH(ARM64)
 
 #include "Common/Log.h"
diff --git a/Core/MIPS/ARM64/Arm64CompLoadStore.cpp b/Core/MIPS/ARM64/Arm64CompLoadStore.cpp
index ca1aae8a8a..92b241d17d 100644
--- a/Core/MIPS/ARM64/Arm64CompLoadStore.cpp
+++ b/Core/MIPS/ARM64/Arm64CompLoadStore.cpp
@@ -311,6 +311,7 @@ namespace MIPSComp {
 		case 40: //sb
 		case 41: //sh
 		case 43: //sw
+#ifndef MASKED_PSP_MEMORY
 			if (jo.cachePointers && g_Config.bFastMemory) {
 				// ARM has smaller load/store immediate displacements than MIPS, 12 bits - and some memory ops only have 8 bits.
 				int offsetRange = 0x3ff;
@@ -327,6 +328,7 @@ namespace MIPSComp {
 						gpr.MapReg(rt, load ? MAP_NOINIT : 0);
 						targetReg = gpr.R(rt);
 					}
+
 					switch (o) {
 					case 35: LDR(INDEX_UNSIGNED, targetReg, gpr.RPtr(rs), offset); break;
 					case 37: LDRH(INDEX_UNSIGNED, targetReg, gpr.RPtr(rs), offset); break;
@@ -342,6 +344,7 @@ namespace MIPSComp {
 					break;
 				}
 			}
+#endif
 
 			if (!load && gpr.IsImm(rt) && gpr.TryMapTempImm(rt) != INVALID_REG) {
 				// We're storing an immediate value, let's see if we can optimize rt.
diff --git a/Core/MIPS/ARM64/Arm64CompVFPU.cpp b/Core/MIPS/ARM64/Arm64CompVFPU.cpp
index 6b6e26eca7..d90ed9bce8 100644
--- a/Core/MIPS/ARM64/Arm64CompVFPU.cpp
+++ b/Core/MIPS/ARM64/Arm64CompVFPU.cpp
@@ -358,7 +358,6 @@ namespace MIPSComp {
 						ADD(SCRATCH1_64, SCRATCH1_64, MEMBASEREG);
 					}
 				}
-
 				fp.STP(32, INDEX_SIGNED, fpr.V(vregs[0]), fpr.V(vregs[1]), SCRATCH1_64, 0);
 				fp.STP(32, INDEX_SIGNED, fpr.V(vregs[2]), fpr.V(vregs[3]), SCRATCH1_64, 8);
 
diff --git a/Core/MIPS/ARM64/Arm64Jit.cpp b/Core/MIPS/ARM64/Arm64Jit.cpp
index cfdb3d0385..6a518cc976 100644
--- a/Core/MIPS/ARM64/Arm64Jit.cpp
+++ b/Core/MIPS/ARM64/Arm64Jit.cpp
@@ -100,6 +100,10 @@ Arm64Jit::Arm64Jit(MIPSState *mips) : blocks(mips, this), gpr(mips, &js, &jo), f
 		jo.enablePointerify = false;
 	}
 
+#ifdef MASKED_PSP_MEMORY
+	jo.enablePointerify = false;
+#endif
+
 	logBlocks = 0;
 	dontLogBlocks = 0;
 	blocks.Init();