Emulation/potatis
1
0
Fork 0
mirror of https://github.com/henrikpersson/potatis.git synced 2025-04-02 10:32:09 -04:00
Code Issues Projects Releases Packages Wiki Activity
potatis/test-roms/bin/functional_test_full.lst
Henrik Persson 61f57a85d9 "First" commit
2022-09-27 21:30:23 +02:00

7012 lines
311 KiB
Text
Raw Permalink Blame History

ca65 V2.18 - N/A
Main file : ./6502_65C02_functional_tests/ca65/6502_functional_test.ca65
Current file: ./6502_65C02_functional_tests/ca65/6502_functional_test.ca65
000000r 1 ;
000000r 1 ; 6 5 0 2 F U N C T I O N A L T E S T
000000r 1 ;
000000r 1 ; Copyright (C) 2012-2020 Klaus Dormann
000000r 1 ;
000000r 1 ; This program is free software: you can redistribute it and/or modify
000000r 1 ; it under the terms of the GNU General Public License as published by
000000r 1 ; the Free Software Foundation, either version 3 of the License, or
000000r 1 ; (at your option) any later version.
000000r 1 ;
000000r 1 ; This program is distributed in the hope that it will be useful,
000000r 1 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
000000r 1 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
000000r 1 ; GNU General Public License for more details.
000000r 1 ;
000000r 1 ; You should have received a copy of the GNU General Public License
000000r 1 ; along with this program. If not, see <http://www.gnu.org/licenses/>.
000000r 1
000000r 1
000000r 1 ; This program is designed to test all opcodes of a 6502 emulator using all
000000r 1 ; addressing modes with focus on propper setting of the processor status
000000r 1 ; register bits.
000000r 1 ;
000000r 1 ; version 05-jan-2020
000000r 1 ; contact info at http://2m5.de or email K@2m5.de
000000r 1 ;
000000r 1 ; assembled with CA65, linked with LD65 (cc65.github.io):
000000r 1 ; ca65 -l 6502_functional_test.lst 6502_functional_test.ca65
000000r 1 ; ld65 6502_functional_test.o -o 6502_functional_test.bin \
000000r 1 ; -m 6502_functional_test.map -C example.cfg
000000r 1 ; example linker config (example.cfg):
000000r 1 ; MEMORY {
000000r 1 ; RAM: start = $0000, size=$8000, type = rw, fill = yes, \
000000r 1 ; fillval = $FF, file = %O;
000000r 1 ; ROM: start = $8000, size=$7FFA, type = ro, fill = yes, \
000000r 1 ; fillval = $FF, file = %O;
000000r 1 ; ROM_VECTORS: start = $FFFA, size=6, type = ro, fill = yes, \
000000r 1 ; fillval = $FF, file = %O;
000000r 1 ; }
000000r 1 ; SEGMENTS {
000000r 1 ; ZEROPAGE: load=RAM, type=rw;
000000r 1 ; DATA: load=RAM, type=rw, offset=$0200;
000000r 1 ; CODE: load=RAM, type=rw, offset=$0400;
000000r 1 ; VECTORS: load=ROM_VECTORS, type=ro;
000000r 1 ; }
000000r 1 ;
000000r 1 ; No IO - should be run from a monitor with access to registers.
000000r 1 ; To run load intel hex image with a load command, than alter PC to 400 hex
000000r 1 ; (code_segment) and enter a go command.
000000r 1 ; Loop on program counter determines error or successful completion of test.
000000r 1 ; Check listing for relevant traps (jump/branch *).
000000r 1 ; Please note that in early tests some instructions will have to be used before
000000r 1 ; they are actually tested!
000000r 1 ;
000000r 1 ; RESET, NMI or IRQ should not occur and will be trapped if vectors are enabled.
000000r 1 ; Tests documented behavior of the original NMOS 6502 only! No unofficial
000000r 1 ; opcodes. Additional opcodes of newer versions of the CPU (65C02, 65816) will
000000r 1 ; not be tested. Decimal ops will only be tested with valid BCD operands and
000000r 1 ; N V Z flags will be ignored.
000000r 1 ;
000000r 1 ; Debugging hints:
000000r 1 ; Most of the code is written sequentially. if you hit a trap, check the
000000r 1 ; immediately preceeding code for the instruction to be tested. Results are
000000r 1 ; tested first, flags are checked second by pushing them onto the stack and
000000r 1 ; pulling them to the accumulator after the result was checked. The "real"
000000r 1 ; flags are no longer valid for the tested instruction at this time!
000000r 1 ; If the tested instruction was indexed, the relevant index (X or Y) must
000000r 1 ; also be checked. Opposed to the flags, X and Y registers are still valid.
000000r 1 ;
000000r 1 ; versions:
000000r 1 ; 28-jul-2012 1st version distributed for testing
000000r 1 ; 29-jul-2012 fixed references to location 0, now #0
000000r 1 ; added license - GPLv3
000000r 1 ; 30-jul-2012 added configuration options
000000r 1 ; 01-aug-2012 added trap macro to allow user to change error handling
000000r 1 ; 01-dec-2012 fixed trap in branch field must be a branch
000000r 1 ; 02-mar-2013 fixed PLA flags not tested
000000r 1 ; 19-jul-2013 allowed ROM vectors to be loaded when load_data_direct = 0
000000r 1 ; added test sequence check to detect if tests jump their fence
000000r 1 ; 23-jul-2013 added RAM integrity check option
000000r 1 ; 16-aug-2013 added error report to standard output option
000000r 1 ; 13-dec-2014 added binary/decimal opcode table switch test
000000r 1 ; 14-dec-2014 improved relative address test
000000r 1 ; 23-aug-2015 added option to disable self modifying tests
000000r 1 ; 24-aug-2015 all self modifying immediate opcodes now execute in data RAM
000000r 1 ; added small branch offset pretest
000000r 1 ; 21-oct-2015 added option to disable decimal mode ADC & SBC tests
000000r 1 ; 04-dec-2017 fixed BRK only tested with interrupts enabled
000000r 1 ; added option to skip the remainder of a failing test
000000r 1 ; in report.i65
000000r 1 ; 05-jan-2020 fixed shifts not testing zero result and flag when last 1-bit
000000r 1 ; is shifted out
000000r 1
000000r 1 ; C O N F I G U R A T I O N
000000r 1
000000r 1 ;ROM_vectors writable (0=no, 1=yes)
000000r 1 ;if ROM vectors can not be used interrupts will not be trapped
000000r 1 ;as a consequence BRK can not be tested but will be emulated to test RTI
000000r 1 ROM_vectors = 1
000000r 1
000000r 1 ;load_data_direct (0=move from code segment, 1=load directly)
000000r 1 ;loading directly is preferred but may not be supported by your platform
000000r 1 ;0 produces only consecutive object code, 1 is not suitable for a binary image
000000r 1 load_data_direct = 1
000000r 1
000000r 1 ;I_flag behavior (0=force enabled, 1=force disabled, 2=prohibit change, 3=allow
000000r 1 ;change) 2 requires extra code and is not recommended. SEI & CLI can only be
000000r 1 ;tested if you allow changing the interrupt status (I_flag = 3)
000000r 1 I_flag = 3
000000r 1
000000r 1 ;configure memory - try to stay away from memory used by the system
000000r 1 ;zero_page memory start address, $52 (82) consecutive Bytes required
000000r 1 ; add 2 if I_flag = 2
000000r 1 zero_page = $a
000000r 1
000000r 1 ;data_segment memory start address, $7B (123) consecutive Bytes required
000000r 1 ; check that this matches the linker configuration file
000000r 1 data_segment = $200
000000r 1 .if (data_segment & $ff) <> 0
000000r 1 .error "low byte of data_segment MUST be $00 !!"
000000r 1 .endif
000000r 1
000000r 1 ;code_segment memory start address, 13.1kB of consecutive space required
000000r 1 ; add 2.5 kB if I_flag = 2
000000r 1 ; check that this matches the linker configuration file
000000r 1 code_segment = $400
000000r 1
000000r 1 ;self modifying code may be disabled to allow running in ROM
000000r 1 ;0=part of the code is self modifying and must reside in RAM
000000r 1 ;1=tests disabled: branch range
000000r 1 disable_selfmod = 0
000000r 1
000000r 1 ;report errors through I/O channel (0=use standard self trap loops, 1=include
000000r 1 ;report.i65 as I/O channel, add 3.5 kB)
000000r 1 report = 0
000000r 1
000000r 1 ;RAM integrity test option. Checks for undesired RAM writes.
000000r 1 ;set lowest non RAM or RAM mirror address page (-1=disable, 0=64k, $40=16k)
000000r 1 ;leave disabled if a monitor, OS or background interrupt is allowed to alter RAM
000000r 1 ram_top = -1
000000r 1
000000r 1 ;disable test decimal mode ADC & SBC, 0=enable, 1=disable,
000000r 1 ;2=disable including decimal flag in processor status
000000r 1 disable_decimal = 0
000000r 1
000000r 1 ;macros for error & success traps to allow user modification
000000r 1 ;example:
000000r 1 ; .macro trap
000000r 1 ; jsr my_error_handler
000000r 1 ; .endmacro
000000r 1 ; .macro trap_eq
000000r 1 ; bne :+
000000r 1 ; trap ;failed equal (zero)
000000r 1 ;:
000000r 1 ; .endmacro
000000r 1 ;
000000r 1 ; my_error_handler should pop the calling address from the stack and report it.
000000r 1 ; putting larger portions of code (more than 3 bytes) inside the trap macro
000000r 1 ; may lead to branch range problems for some tests.
000000r 1 .if report = 0
000000r 1 .macro trap
000000r 1 jmp * ;failed anyway
000000r 1 .endmacro
000000r 1 .macro trap_eq
000000r 1 beq * ;failed equal (zero)
000000r 1 .endmacro
000000r 1 .macro trap_ne
000000r 1 bne * ;failed not equal (non zero)
000000r 1 .endmacro
000000r 1 .macro trap_cs
000000r 1 bcs * ;failed carry set
000000r 1 .endmacro
000000r 1 .macro trap_cc
000000r 1 bcc * ;failed carry clear
000000r 1 .endmacro
000000r 1 .macro trap_mi
000000r 1 bmi * ;failed minus (bit 7 set)
000000r 1 .endmacro
000000r 1 .macro trap_pl
000000r 1 bpl * ;failed plus (bit 7 clear)
000000r 1 .endmacro
000000r 1 .macro trap_vs
000000r 1 bvs * ;failed overflow set
000000r 1 .endmacro
000000r 1 .macro trap_vc
000000r 1 bvc * ;failed overflow clear
000000r 1 .endmacro
000000r 1 ; please observe that during the test the stack gets invalidated
000000r 1 ; therefore a RTS inside the success macro is not possible
000000r 1 .macro success
000000r 1 jmp * ;test passed, no errors
000000r 1 .endmacro
000000r 1 .endif
000000r 1 .if report = 1
000000r 1 .macro trap
000000r 1 jsr report_error
000000r 1 .endmacro
000000r 1 .macro trap_eq
000000r 1 bne :+
000000r 1 trap ;failed equal (zero)
000000r 1 :
000000r 1 .endmacro
000000r 1 .macro trap_ne
000000r 1 beq :+
000000r 1 trap ;failed not equal (non zero)
000000r 1 :
000000r 1 .endmacro
000000r 1 .macro trap_cs
000000r 1 bcc :+
000000r 1 trap ;failed carry set
000000r 1 :
000000r 1 .endmacro
000000r 1 .macro trap_cc
000000r 1 bcs :+
000000r 1 trap ;failed carry clear
000000r 1 :
000000r 1 .endmacro
000000r 1 .macro trap_mi
000000r 1 bpl :+
000000r 1 trap ;failed minus (bit 7 set)
000000r 1 :
000000r 1 .endmacro
000000r 1 .macro trap_pl
000000r 1 bmi :+
000000r 1 trap ;failed plus (bit 7 clear)
000000r 1 :
000000r 1 .endmacro
000000r 1 .macro trap_vs
000000r 1 bvc :+
000000r 1 trap ;failed overflow set
000000r 1 :
000000r 1 .endmacro
000000r 1 .macro trap_vc
000000r 1 bvs :+
000000r 1 trap ;failed overflow clear
000000r 1 :
000000r 1 .endmacro
000000r 1 ; please observe that during the test the stack gets invalidated
000000r 1 ; therefore a RTS inside the success macro is not possible
000000r 1 .macro success
000000r 1 jsr report_success
000000r 1 .endmacro
000000r 1 .endif
000000r 1
000000r 1 .define equ =
000000r 1
000000r 1 carry equ %00000001 ;flag bits in status
000000r 1 zero equ %00000010
000000r 1 intdis equ %00000100
000000r 1 decmode equ %00001000
000000r 1 break equ %00010000
000000r 1 reserv equ %00100000
000000r 1 overfl equ %01000000
000000r 1 minus equ %10000000
000000r 1
000000r 1 fc equ carry
000000r 1 fz equ zero
000000r 1 fzc equ carry+zero
000000r 1 fv equ overfl
000000r 1 fvz equ overfl+zero
000000r 1 fn equ minus
000000r 1 fnc equ minus+carry
000000r 1 fnz equ minus+zero
000000r 1 fnzc equ minus+zero+carry
000000r 1 fnv equ minus+overfl
000000r 1
000000r 1 fao equ break+reserv ;bits always on after PHP, BRK
000000r 1 fai equ fao+intdis ;+ forced interrupt disable
000000r 1 faod equ fao+decmode ;+ ignore decimal
000000r 1 faid equ fai+decmode ;+ ignore decimal
000000r 1 m8 equ $ff ;8 bit mask
000000r 1 m8i equ $ff&~intdis ;8 bit mask - interrupt disable
000000r 1
000000r 1 ;macros to allow masking of status bits.
000000r 1 ;masking test of decimal bit
000000r 1 ;masking of interrupt enable/disable on load and compare
000000r 1 ;masking of always on bits after PHP or BRK (unused & break) on compare
000000r 1 .if disable_decimal < 2
000000r 1 .if I_flag = 0
000000r 1 .macro load_flag p1
000000r 1 lda #p1&m8i ;force enable interrupts (mask I)
000000r 1 .endmacro
000000r 1 .macro cmp_flag p1
000000r 1 cmp #(p1|fao)&m8i ;I_flag is always enabled + always on bits
000000r 1 .endmacro
000000r 1 .macro eor_flag p1
000000r 1 eor #(p1&m8i|fao) ;mask I, invert expected flags + always on bits
000000r 1 .endmacro
000000r 1 .endif
000000r 1 .if I_flag = 1
000000r 1 .macro load_flag p1
000000r 1 lda #p1|intdis ;force disable interrupts
000000r 1 .endmacro
000000r 1 .macro cmp_flag p1
000000r 1 cmp #(p1|fai)&m8 ;I_flag is always disabled + always on bits
000000r 1 .endmacro
000000r 1 .macro eor_flag p1
000000r 1 eor #(p1|fai) ;invert expected flags + always on bits + I
000000r 1 .endmacro
000000r 1 .endif
000000r 1 .if I_flag = 2
000000r 1 .macro load_flag p1
000000r 1 lda #p1
000000r 1 ora flag_I_on ;restore I-flag
000000r 1 and flag_I_off
000000r 1 .endmacro
000000r 1 .macro cmp_flag p1
000000r 1 eor flag_I_on ;I_flag is never changed
000000r 1 cmp #(p1|fao)&m8i ;expected flags + always on bits, mask I
000000r 1 .endmacro
000000r 1 .macro eor_flag p1
000000r 1 eor flag_I_on ;I_flag is never changed
000000r 1 eor #(p1&m8i|fao) ;mask I, invert expected flags + always on bits
000000r 1 .endmacro
000000r 1 .endif
000000r 1 .if I_flag = 3
000000r 1 .macro load_flag p1
000000r 1 lda #p1 ;allow test to change I-flag (no mask)
000000r 1 .endmacro
000000r 1 .macro cmp_flag p1
000000r 1 cmp #(p1|fao)&m8 ;expected flags + always on bits
000000r 1 .endmacro
000000r 1 .macro eor_flag p1
000000r 1 eor #p1|fao ;invert expected flags + always on bits
000000r 1 .endmacro
000000r 1 .endif
000000r 1 .else
000000r 1 .if I_flag = 0
000000r 1 .macro load_flag p1
000000r 1 lda #p1&m8i ;force enable interrupts (mask I)
000000r 1 .endmacro
000000r 1 .macro cmp_flag p1
000000r 1 ora #decmode ;ignore decimal mode bit
000000r 1 cmp #(p1|faod)&m8i ;I_flag is always enabled + always on bits
000000r 1 .endmacro
000000r 1 .macro eor_flag p1
000000r 1 ora #decmode ;ignore decimal mode bit
000000r 1 eor #(p1&m8i|faod) ;mask I, invert expected flags + always on bits
000000r 1 .endmacro
000000r 1 .endif
000000r 1 .if I_flag = 1
000000r 1 .macro load_flag p1
000000r 1 lda #p1|intdis ;force disable interrupts
000000r 1 .endmacro
000000r 1 .macro cmp_flag p1
000000r 1 ora #decmode ;ignore decimal mode bit
000000r 1 cmp #(p1|faid)&m8 ;I_flag is always disabled + always on bits
000000r 1 .endmacro
000000r 1 .macro eor_flag p1
000000r 1 ora #decmode ;ignore decimal mode bit
000000r 1 eor #(p1|faid) ;invert expected flags + always on bits + I
000000r 1 .endmacro
000000r 1 .endif
000000r 1 .if I_flag = 2
000000r 1 .macro load_flag p1
000000r 1 lda #p1
000000r 1 ora flag_I_on ;restore I-flag
000000r 1 and flag_I_off
000000r 1 .endmacro
000000r 1 .macro cmp_flag p1
000000r 1 eor flag_I_on ;I_flag is never changed
000000r 1 ora #decmode ;ignore decimal mode bit
000000r 1 cmp #(p1|faod)&m8i ;expected flags + always on bits, mask I
000000r 1 .endmacro
000000r 1 .macro eor_flag p1
000000r 1 eor flag_I_on ;I_flag is never changed
000000r 1 ora #decmode ;ignore decimal mode bit
000000r 1 eor #(p1&m8i|faod) ;mask I, invert expected flags + always on bits
000000r 1 .endmacro
000000r 1 .endif
000000r 1 .if I_flag = 3
000000r 1 .macro load_flag p1
000000r 1 lda #p1 ;allow test to change I-flag (no mask)
000000r 1 .endmacro
000000r 1 .macro cmp_flag p1
000000r 1 ora #decmode ;ignore decimal mode bit
000000r 1 cmp #(p1|faod)&m8 ;expected flags + always on bits
000000r 1 .endmacro
000000r 1 .macro eor_flag p1
000000r 1 ora #decmode ;ignore decimal mode bit
000000r 1 eor #p1|faod ;invert expected flags + always on bits
000000r 1 .endmacro
000000r 1 .endif
000000r 1 .endif
000000r 1
000000r 1 ;macros to set (register|memory|zeropage) & status
000000r 1 .macro set_stat p1 ;setting flags in the processor status register
000000r 1 load_flag p1
000000r 1 pha ;use stack to load status
000000r 1 plp
000000r 1 .endmacro
000000r 1
000000r 1 .macro set_a p1,p2 ;precharging accu & status
000000r 1 load_flag p2
000000r 1 pha ;use stack to load status
000000r 1 lda #p1 ;precharge accu
000000r 1 plp
000000r 1 .endmacro
000000r 1
000000r 1 .macro set_x p1,p2 ;precharging index & status
000000r 1 load_flag p2
000000r 1 pha ;use stack to load status
000000r 1 ldx #p1 ;precharge index x
000000r 1 plp
000000r 1 .endmacro
000000r 1
000000r 1 .macro set_y p1,p2 ;precharging index & status
000000r 1 load_flag p2
000000r 1 pha ;use stack to load status
000000r 1 ldy #p1 ;precharge index y
000000r 1 plp
000000r 1 .endmacro
000000r 1
000000r 1 .macro set_ax p1,p2 ;precharging indexed accu & immediate status
000000r 1 load_flag p2
000000r 1 pha ;use stack to load status
000000r 1 lda p1,x ;precharge accu
000000r 1 plp
000000r 1 .endmacro
000000r 1
000000r 1 .macro set_ay p1,p2 ;precharging indexed accu & immediate status
000000r 1 load_flag p2
000000r 1 pha ;use stack to load status
000000r 1 lda p1,y ;precharge accu
000000r 1 plp
000000r 1 .endmacro
000000r 1
000000r 1 .macro set_z p1,p2 ;precharging indexed zp & immediate status
000000r 1 load_flag p2
000000r 1 pha ;use stack to load status
000000r 1 lda p1,x ;load to zeropage
000000r 1 sta zpt
000000r 1 plp
000000r 1 .endmacro
000000r 1
000000r 1 .macro set_zx p1,p2 ;precharging zp,x & immediate status
000000r 1 load_flag p2
000000r 1 pha ;use stack to load status
000000r 1 lda p1,x ;load to indexed zeropage
000000r 1 sta zpt,x
000000r 1 plp
000000r 1 .endmacro
000000r 1
000000r 1 .macro set_abs p1,p2 ;precharging indexed memory & immediate status
000000r 1 load_flag p2
000000r 1 pha ;use stack to load status
000000r 1 lda p1,x ;load to memory
000000r 1 sta abst
000000r 1 plp
000000r 1 .endmacro
000000r 1
000000r 1 .macro set_absx p1,p2 ;precharging abs,x & immediate status
000000r 1 load_flag p2
000000r 1 pha ;use stack to load status
000000r 1 lda p1,x ;load to indexed memory
000000r 1 sta abst,x
000000r 1 plp
000000r 1 .endmacro
000000r 1
000000r 1 ;macros to test (register|memory|zeropage) & status & (mask)
000000r 1 .macro tst_stat p1 ;testing flags in the processor status register
000000r 1 php ;save status
000000r 1 pla ;use stack to retrieve status
000000r 1 pha
000000r 1 cmp_flag p1
000000r 1 trap_ne
000000r 1 plp ;restore status
000000r 1 .endmacro
000000r 1
000000r 1 .macro tst_a p1,p2 ;testing result in accu & flags
000000r 1 php ;save flags
000000r 1 cmp #p1 ;test result
000000r 1 trap_ne
000000r 1 pla ;load status
000000r 1 pha
000000r 1 cmp_flag p2
000000r 1 trap_ne
000000r 1 plp ;restore status
000000r 1 .endmacro
000000r 1
000000r 1 .macro tst_x p1,p2 ;testing result in x index & flags
000000r 1 php ;save flags
000000r 1 cpx #p1 ;test result
000000r 1 trap_ne
000000r 1 pla ;load status
000000r 1 pha
000000r 1 cmp_flag p2
000000r 1 trap_ne
000000r 1 plp ;restore status
000000r 1 .endmacro
000000r 1
000000r 1 .macro tst_y p1,p2 ;testing result in y index & flags
000000r 1 php ;save flags
000000r 1 cpy #p1 ;test result
000000r 1 trap_ne
000000r 1 pla ;load status
000000r 1 pha
000000r 1 cmp_flag p2
000000r 1 trap_ne
000000r 1 plp ;restore status
000000r 1 .endmacro
000000r 1
000000r 1 .macro tst_ax p1,p2,p3 ;indexed testing result in accu & flags
000000r 1 php ;save flags
000000r 1 cmp p1,x ;test result
000000r 1 trap_ne
000000r 1 pla ;load status
000000r 1 eor_flag p3
000000r 1 cmp p2,x ;test flags
000000r 1 trap_ne ;
000000r 1 .endmacro
000000r 1
000000r 1 .macro tst_ay p1,p2,p3 ;indexed testing result in accu & flags
000000r 1 php ;save flags
000000r 1 cmp p1,y ;test result
000000r 1 trap_ne ;
000000r 1 pla ;load status
000000r 1 eor_flag p3
000000r 1 cmp p2,y ;test flags
000000r 1 trap_ne
000000r 1 .endmacro
000000r 1
000000r 1 .macro tst_z p1,p2,p3 ;indexed testing result in zp & flags
000000r 1 php ;save flags
000000r 1 lda zpt
000000r 1 cmp p1,x ;test result
000000r 1 trap_ne
000000r 1 pla ;load status
000000r 1 eor_flag p3
000000r 1 cmp p2,x ;test flags
000000r 1 trap_ne
000000r 1 .endmacro
000000r 1
000000r 1 .macro tst_zx p1,p2,p3 ;testing result in zp,x & flags
000000r 1 php ;save flags
000000r 1 lda zpt,x
000000r 1 cmp p1,x ;test result
000000r 1 trap_ne
000000r 1 pla ;load status
000000r 1 eor_flag p3
000000r 1 cmp p2,x ;test flags
000000r 1 trap_ne
000000r 1 .endmacro
000000r 1
000000r 1 .macro tst_abs p1,p2,p3 ;indexed testing result in memory & flags
000000r 1 php ;save flags
000000r 1 lda abst
000000r 1 cmp p1,x ;test result
000000r 1 trap_ne
000000r 1 pla ;load status
000000r 1 eor_flag p3
000000r 1 cmp p2,x ;test flags
000000r 1 trap_ne
000000r 1 .endmacro
000000r 1
000000r 1 .macro tst_absx p1,p2,p3 ;testing result in abs,x & flags
000000r 1 php ;save flags
000000r 1 lda abst,x
000000r 1 cmp p1,x ;test result
000000r 1 trap_ne
000000r 1 pla ;load status
000000r 1 eor_flag p3
000000r 1 cmp p2,x ;test flags
000000r 1 trap_ne
000000r 1 .endmacro
000000r 1
000000r 1 ; RAM integrity test
000000r 1 ; verifies that none of the previous tests has altered RAM outside of the
000000r 1 ; designated write areas.
000000r 1 ; uses zpt word as indirect pointer, zpt+2 word as checksum
000000r 1 .if ram_top > -1
000000r 1 check_ram macro
000000r 1 cld
000000r 1 lda #0
000000r 1 sta zpt ;set low byte of indirect pointer
000000r 1 sta zpt+3 ;checksum high byte
000000r 1 .if disable_selfmod = 0
000000r 1 sta range_adr ;reset self modifying code
000000r 1 .endif
000000r 1 clc
000000r 1 ldx #zp_bss-zero_page ;zeropage - write test area
000000r 1 ccs3: adc zero_page,x
000000r 1 bcc ccs2
000000r 1 inc zpt+3 ;carry to high byte
000000r 1 clc
000000r 1 ccs2: inx
000000r 1 bne ccs3
000000r 1 ldx #hi(abs1) ;set high byte of indirect pointer
000000r 1 stx zpt+1
000000r 1 ldy #lo(abs1) ;data after write & execute test area
000000r 1 ccs5: adc (zpt),y
000000r 1 bcc ccs4
000000r 1 inc zpt+3 ;carry to high byte
000000r 1 clc
000000r 1 ccs4: iny
000000r 1 bne ccs5
000000r 1 inx ;advance RAM high address
000000r 1 stx zpt+1
000000r 1 cpx #ram_top
000000r 1 bne ccs5
000000r 1 sta zpt+2 ;checksum low is
000000r 1 cmp ram_chksm ;checksum low expected
000000r 1 trap_ne ;checksum mismatch
000000r 1 lda zpt+3 ;checksum high is
000000r 1 cmp ram_chksm+1 ;checksum high expected
000000r 1 trap_ne ;checksum mismatch
000000r 1 .endmacro
000000r 1 .else
000000r 1 .macro check_ram
000000r 1 ;RAM check disabled - RAM size not set
000000r 1 .endmacro
000000r 1 .endif
000000r 1
000000r 1 .macro next_test ;make sure, tests don't jump the fence
000000r 1 lda test_case ;previous test
000000r 1 cmp #test_num
000000r 1 trap_ne ;test is out of sequence
000000r 1 test_num .set test_num + 1
000000r 1 lda #test_num ;*** next tests' number
000000r 1 sta test_case
000000r 1 ;check_ram ;uncomment to find altered RAM after each test
000000r 1 .endmacro
000000r 1
000000r 1 .ZEROPAGE
000000r 1 00 00 00 00 .res zero_page, 0
000004r 1 00 00 00 00
000008r 1 00 00
00000Ar 1 .org zero_page
00000A 1
00000A 1 ;break test interrupt save
00000A 1 00 irq_a: .res 1,0 ;a register
00000B 1 00 irq_x: .res 1,0 ;x register
00000C 1 .if I_flag = 2
00000C 1 ;masking for I bit in status
00000C 1 flag_I_on: .res 1,0 ;or mask to load flags
00000C 1 flag_I_off: .res 1,0 ;and mask to load flags
00000C 1 .endif
00000C 1 zpt: ;6 bytes store/modify test area
00000C 1 ;add/subtract operand generation and result/flag prediction
00000C 1 00 adfc: .res 1,0 ;carry flag before op
00000D 1 00 ad1: .res 1,0 ;operand 1 - accumulator
00000E 1 00 ad2: .res 1,0 ;operand 2 - memory / immediate
00000F 1 00 adrl: .res 1,0 ;expected result bits 0-7
000010 1 00 adrh: .res 1,0 ;expected result bit 8 (carry)
000011 1 00 adrf: .res 1,0 ;expected flags NV0000ZC (only binary mode)
000012 1 00 sb2: .res 1,0 ;operand 2 complemented for subtract
000013 1 zp_bss:
000013 1 80 01 zps: .byte $80,1 ;additional shift pattern to test zero result & flag
000015 1 C3 82 41 00 zp1: .byte $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
000019 1 7F zp7f: .byte $7f ;test pattern for compare
00001A 1 ;logical zeropage operands
00001A 1 00 1F 71 80 zpOR: .byte 0,$1f,$71,$80 ;test pattern for OR
00001E 1 0F FF 7F 80 zpAN: .byte $0f,$ff,$7f,$80 ;test pattern for AND
000022 1 FF 0F 8F 8F zpEO: .byte $ff,$0f,$8f,$8f ;test pattern for EOR
000026 1 ;indirect addressing pointers
000026 1 18 02 ind1: .word abs1 ;indirect pointer to pattern in absolute memory
000028 1 19 02 .word abs1+1
00002A 1 1A 02 .word abs1+2
00002C 1 1B 02 .word abs1+3
00002E 1 1C 02 .word abs7f
000030 1 20 01 inw1: .word abs1-$f8 ;indirect pointer for wrap-test pattern
000032 1 03 02 indt: .word abst ;indirect pointer to store area in absolute memory
000034 1 04 02 .word abst+1
000036 1 05 02 .word abst+2
000038 1 06 02 .word abst+3
00003A 1 0B 01 inwt: .word abst-$f8 ;indirect pointer for wrap-test store
00003C 1 5F 02 indAN: .word absAN ;indirect pointer to AND pattern in absolute memory
00003E 1 60 02 .word absAN+1
000040 1 61 02 .word absAN+2
000042 1 62 02 .word absAN+3
000044 1 63 02 indEO: .word absEO ;indirect pointer to EOR pattern in absolute memory
000046 1 64 02 .word absEO+1
000048 1 65 02 .word absEO+2
00004A 1 66 02 .word absEO+3
00004C 1 5B 02 indOR: .word absOR ;indirect pointer to OR pattern in absolute memory
00004E 1 5C 02 .word absOR+1
000050 1 5D 02 .word absOR+2
000052 1 5E 02 .word absOR+3
000054 1 ;add/subtract indirect pointers
000054 1 03 02 adi2: .word ada2 ;indirect pointer to operand 2 in absolute memory
000056 1 04 02 sbi2: .word sba2 ;indirect pointer to complemented operand 2 (SBC)
000058 1 04 01 adiy2: .word ada2-$ff ;with offset for indirect indexed
00005A 1 05 01 sbiy2: .word sba2-$ff
00005C 1 zp_bss_end:
00005C 1
00005C 1 .DATA
00005C 1 .org data_segment
000200 1
000200 1 00 test_case: .res 1,0 ;current test number
000201 1 00 00 ram_chksm: .res 2,0 ;checksum for RAM integrity test
000203 1 ;add/subtract operand copy - abs tests write area
000203 1 abst: ;6 bytes store/modify test area
000203 1 00 ada2: .res 1,0 ;operand 2
000204 1 00 sba2: .res 1,0 ;operand 2 complemented for subtract
000205 1 00 00 00 00 .res 4,0 ;fill remaining bytes
000209 1 data_bss:
000209 1 .if load_data_direct = 1
000209 1 29 00 ex_andi:and #0 ;execute immediate opcodes
00020B 1 60 rts
00020C 1 49 00 ex_eori:eor #0 ;execute immediate opcodes
00020E 1 60 rts
00020F 1 09 00 ex_orai:ora #0 ;execute immediate opcodes
000211 1 60 rts
000212 1 69 00 ex_adci:adc #0 ;execute immediate opcodes
000214 1 60 rts
000215 1 E9 00 ex_sbci:sbc #0 ;execute immediate opcodes
000217 1 60 rts
000218 1 .else
000218 1 ex_andi:.res 3
000218 1 ex_eori:.res 3
000218 1 ex_orai:.res 3
000218 1 ex_adci:.res 3
000218 1 ex_sbci:.res 3
000218 1 .endif
000218 1 ;zps .byte $80,1 ;additional shift patterns test zero result & flag
000218 1 C3 82 41 00 abs1: .byte $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
00021C 1 7F abs7f: .byte $7f ;test pattern for compare
00021D 1 ;loads
00021D 1 80 80 00 02 fLDx: .byte fn,fn,0,fz ;expected flags for load
000221 1 ;shifts
000221 1 rASL: ;expected result ASL & ROL -carry
000221 1 00 02 86 04 rROL: .byte 0,2,$86,$04,$82,0
000225 1 82 00
000227 1 01 03 87 05 rROLc: .byte 1,3,$87,$05,$83,1 ;expected result ROL +carry
00022B 1 83 01
00022D 1 rLSR: ;expected result LSR & ROR -carry
00022D 1 40 00 61 41 rROR: .byte $40,0,$61,$41,$20,0
000231 1 20 00
000233 1 C0 80 E1 C1 rRORc: .byte $c0,$80,$e1,$c1,$a0,$80 ;expected result ROR +carry
000237 1 A0 80
000239 1 fASL: ;expected flags for shifts
000239 1 03 00 81 01 fROL: .byte fzc,0,fnc,fc,fn,fz ;no carry in
00023D 1 80 02
00023F 1 01 00 81 01 fROLc: .byte fc,0,fnc,fc,fn,0 ;carry in
000243 1 80 00
000245 1 fLSR:
000245 1 00 03 01 00 fROR: .byte 0,fzc,fc,0,fc,fz ;no carry in
000249 1 01 02
00024B 1 80 81 81 80 fRORc: .byte fn,fnc,fnc,fn,fnc,fn ;carry in
00024F 1 81 80
000251 1 ;increments (decrements)
000251 1 7F 80 FF 00 rINC: .byte $7f,$80,$ff,0,1 ;expected result for INC/DEC
000255 1 01
000256 1 00 80 80 02 fINC: .byte 0,fn,fn,fz,0 ;expected flags for INC/DEC
00025A 1 00
00025B 1 ;logical memory operand
00025B 1 00 1F 71 80 absOR: .byte 0,$1f,$71,$80 ;test pattern for OR
00025F 1 0F FF 7F 80 absAN: .byte $0f,$ff,$7f,$80 ;test pattern for AND
000263 1 FF 0F 8F 8F absEO: .byte $ff,$0f,$8f,$8f ;test pattern for EOR
000267 1 ;logical accu operand
000267 1 00 F1 1F 00 absORa: .byte 0,$f1,$1f,0 ;test pattern for OR
00026B 1 F0 FF FF FF absANa: .byte $f0,$ff,$ff,$ff ;test pattern for AND
00026F 1 FF F0 F0 0F absEOa: .byte $ff,$f0,$f0,$0f ;test pattern for EOR
000273 1 ;logical results
000273 1 00 FF 7F 80 absrlo: .byte 0,$ff,$7f,$80
000277 1 02 80 00 80 absflo: .byte fz,fn,0,fn
00027B 1 data_bss_end:
00027B 1
00027B 1
00027B 1 .CODE
00027B 1 .org code_segment
000400 1 .P02 ; disable 65SC02, 65C02 and 65816 instructions
000400 1 D8 start: cld
000401 1 A2 FF ldx #$ff
000403 1 9A txs
000404 1 A9 00 lda #0 ;*** test 0 = initialize
000406 1 8D 00 02 sta test_case
000409 1 test_num .set 0
000409 1
000409 1 ;stop interrupts before initializing BSS
000409 1 .if I_flag = 1
000409 1 sei
000409 1 .endif
000409 1
000409 1 ;initialize I/O for report channel
000409 1 .if report = 1
000409 1 jsr report_init
000409 1 .endif
000409 1
000409 1 ;pretest small branch offset
000409 1 A2 05 ldx #5
00040B 1 4C 33 04 jmp psb_test
00040E 1 psb_bwok:
00040E 1 A0 05 ldy #5
000410 1 D0 08 bne psb_forw
000412 1 4C 12 04 trap ;branch should be taken
000415 1 88 dey ;forward landing zone
000416 1 88 dey
000417 1 88 dey
000418 1 88 dey
000419 1 88 dey
00041A 1 psb_forw:
00041A 1 88 dey
00041B 1 88 dey
00041C 1 88 dey
00041D 1 88 dey
00041E 1 88 dey
00041F 1 F0 17 beq psb_fwok
000421 1 4C 21 04 trap ;forward offset
000424 1
000424 1 CA dex ;backward landing zone
000425 1 CA dex
000426 1 CA dex
000427 1 CA dex
000428 1 CA dex
000429 1 psb_back:
000429 1 CA dex
00042A 1 CA dex
00042B 1 CA dex
00042C 1 CA dex
00042D 1 CA dex
00042E 1 F0 DE beq psb_bwok
000430 1 4C 30 04 trap ;backward offset
000433 1 psb_test:
000433 1 D0 F4 bne psb_back
000435 1 4C 35 04 trap ;branch should be taken
000438 1 psb_fwok:
000438 1
000438 1 ;initialize BSS segment
000438 1 .if load_data_direct <> 1
000438 1 ldx #zp_end-zp_init-1
000438 1 ld_zp: lda zp_init,x
000438 1 sta zp_bss,x
000438 1 dex
000438 1 bpl ld_zp
000438 1 ldx #data_end-data_init-1
000438 1 ld_data:lda data_init,x
000438 1 sta data_bss,x
000438 1 dex
000438 1 bpl ld_data
000438 1 .if ROM_vectors = 1
000438 1 ldx #5
000438 1 ld_vect:lda vec_init,x
000438 1 sta vec_bss,x
000438 1 dex
000438 1 bpl ld_vect
000438 1 .endif
000438 1 .endif
000438 1
000438 1 ;retain status of interrupt flag
000438 1 .if I_flag = 2
000438 1 php
000438 1 pla
000438 1 and #4 ;isolate flag
000438 1 sta flag_I_on ;or mask
000438 1 eor #lo(~4) ;reverse
000438 1 sta flag_I_off ;and mask
000438 1 .endif
000438 1
000438 1 ;generate checksum for RAM integrity test
000438 1 .if ram_top > -1
000438 1 lda #0
000438 1 sta zpt ;set low byte of indirect pointer
000438 1 sta ram_chksm+1 ;checksum high byte
000438 1 .if disable_selfmod = 0
000438 1 sta range_adr ;reset self modifying code
000438 1 .endif
000438 1 clc
000438 1 ldx #zp_bss-zero_page ;zeropage - write test area
000438 1 gcs3: adc zero_page,x
000438 1 bcc gcs2
000438 1 inc ram_chksm+1 ;carry to high byte
000438 1 clc
000438 1 gcs2: inx
000438 1 bne gcs3
000438 1 ldx #hi(abs1) ;set high byte of indirect pointer
000438 1 stx zpt+1
000438 1 ldy #lo(abs1) ;data after write & execute test area
000438 1 gcs5: adc (zpt),y
000438 1 bcc gcs4
000438 1 inc ram_chksm+1 ;carry to high byte
000438 1 clc
000438 1 gcs4: iny
000438 1 bne gcs5
000438 1 inx ;advance RAM high address
000438 1 stx zpt+1
000438 1 cpx #ram_top
000438 1 bne gcs5
000438 1 sta ram_chksm ;checksum complete
000438 1 .endif
000438 1 AD 00 02 C9 next_test
00043C 1 00 D0 FE A9
000440 1 01 8D 00 02
000444 1
000444 1 .if disable_selfmod = 0
000444 1 ;testing relative addressing with BEQ
000444 1 A0 FE ldy #$fe ;testing maximum range, not -1/-2 (invalid/self adr)
000446 1 range_loop:
000446 1 88 dey ;next relative address
000447 1 98 tya
000448 1 AA tax ;precharge count to end of loop
000449 1 10 08 bpl range_fw ;calculate relative address
00044B 1 18 clc ;avoid branch self or to relative address of branch
00044C 1 69 02 adc #2
00044E 1 EA nop ;offset landing zone - tolerate +/-5 offset to branch
00044F 1 EA nop
000450 1 EA nop
000451 1 EA nop
000452 1 EA nop
000453 1 range_fw:
000453 1 EA nop
000454 1 EA nop
000455 1 EA nop
000456 1 EA nop
000457 1 EA nop
000458 1 49 7F eor #$7f ;complement except sign
00045A 1 8D E6 04 sta range_adr ;load into test target
00045D 1 A9 00 lda #0 ;should set zero flag in status register
00045F 1 4C E5 04 jmp range_op
000462 1
000462 1 CA dex ; offset landing zone - backward branch too far
000463 1 CA dex
000464 1 CA dex
000465 1 CA dex
000466 1 CA dex
000467 1 ;relative address target field with branch under test in the middle
000467 1 CA dex ;-128 - max backward
000468 1 CA dex
000469 1 CA dex
00046A 1 CA dex
00046B 1 CA dex
00046C 1 CA dex
00046D 1 CA dex
00046E 1 CA dex
00046F 1 CA dex ;-120
000470 1 CA dex
000471 1 CA dex
000472 1 CA dex
000473 1 CA dex
000474 1 CA dex
000475 1 CA dex
000476 1 CA dex
000477 1 CA dex
000478 1 CA dex
000479 1 CA dex ;-110
00047A 1 CA dex
00047B 1 CA dex
00047C 1 CA dex
00047D 1 CA dex
00047E 1 CA dex
00047F 1 CA dex
000480 1 CA dex
000481 1 CA dex
000482 1 CA dex
000483 1 CA dex ;-100
000484 1 CA dex
000485 1 CA dex
000486 1 CA dex
000487 1 CA dex
000488 1 CA dex
000489 1 CA dex
00048A 1 CA dex
00048B 1 CA dex
00048C 1 CA dex
00048D 1 CA dex ;-90
00048E 1 CA dex
00048F 1 CA dex
000490 1 CA dex
000491 1 CA dex
000492 1 CA dex
000493 1 CA dex
000494 1 CA dex
000495 1 CA dex
000496 1 CA dex
000497 1 CA dex ;-80
000498 1 CA dex
000499 1 CA dex
00049A 1 CA dex
00049B 1 CA dex
00049C 1 CA dex
00049D 1 CA dex
00049E 1 CA dex
00049F 1 CA dex
0004A0 1 CA dex
0004A1 1 CA dex ;-70
0004A2 1 CA dex
0004A3 1 CA dex
0004A4 1 CA dex
0004A5 1 CA dex
0004A6 1 CA dex
0004A7 1 CA dex
0004A8 1 CA dex
0004A9 1 CA dex
0004AA 1 CA dex
0004AB 1 CA dex ;-60
0004AC 1 CA dex
0004AD 1 CA dex
0004AE 1 CA dex
0004AF 1 CA dex
0004B0 1 CA dex
0004B1 1 CA dex
0004B2 1 CA dex
0004B3 1 CA dex
0004B4 1 CA dex
0004B5 1 CA dex ;-50
0004B6 1 CA dex
0004B7 1 CA dex
0004B8 1 CA dex
0004B9 1 CA dex
0004BA 1 CA dex
0004BB 1 CA dex
0004BC 1 CA dex
0004BD 1 CA dex
0004BE 1 CA dex
0004BF 1 CA dex ;-40
0004C0 1 CA dex
0004C1 1 CA dex
0004C2 1 CA dex
0004C3 1 CA dex
0004C4 1 CA dex
0004C5 1 CA dex
0004C6 1 CA dex
0004C7 1 CA dex
0004C8 1 CA dex
0004C9 1 CA dex ;-30
0004CA 1 CA dex
0004CB 1 CA dex
0004CC 1 CA dex
0004CD 1 CA dex
0004CE 1 CA dex
0004CF 1 CA dex
0004D0 1 CA dex
0004D1 1 CA dex
0004D2 1 CA dex
0004D3 1 CA dex ;-20
0004D4 1 CA dex
0004D5 1 CA dex
0004D6 1 CA dex
0004D7 1 CA dex
0004D8 1 CA dex
0004D9 1 CA dex
0004DA 1 CA dex
0004DB 1 CA dex
0004DC 1 CA dex
0004DD 1 CA dex ;-10
0004DE 1 CA dex
0004DF 1 CA dex
0004E0 1 CA dex
0004E1 1 CA dex
0004E2 1 CA dex
0004E3 1 CA dex
0004E4 1 CA dex ;-3
0004E5 1 range_op: ;test target with zero flag=0, z=1 if previous dex
0004E5 1 range_adr = *+1 ;modifiable relative address
0004E5 1 F0 3E beq *+64 ;+64 if called without modification
0004E7 1 CA dex ;+0
0004E8 1 CA dex
0004E9 1 CA dex
0004EA 1 CA dex
0004EB 1 CA dex
0004EC 1 CA dex
0004ED 1 CA dex
0004EE 1 CA dex
0004EF 1 CA dex
0004F0 1 CA dex
0004F1 1 CA dex ;+10
0004F2 1 CA dex
0004F3 1 CA dex
0004F4 1 CA dex
0004F5 1 CA dex
0004F6 1 CA dex
0004F7 1 CA dex
0004F8 1 CA dex
0004F9 1 CA dex
0004FA 1 CA dex
0004FB 1 CA dex ;+20
0004FC 1 CA dex
0004FD 1 CA dex
0004FE 1 CA dex
0004FF 1 CA dex
000500 1 CA dex
000501 1 CA dex
000502 1 CA dex
000503 1 CA dex
000504 1 CA dex
000505 1 CA dex ;+30
000506 1 CA dex
000507 1 CA dex
000508 1 CA dex
000509 1 CA dex
00050A 1 CA dex
00050B 1 CA dex
00050C 1 CA dex
00050D 1 CA dex
00050E 1 CA dex
00050F 1 CA dex ;+40
000510 1 CA dex
000511 1 CA dex
000512 1 CA dex
000513 1 CA dex
000514 1 CA dex
000515 1 CA dex
000516 1 CA dex
000517 1 CA dex
000518 1 CA dex
000519 1 CA dex ;+50
00051A 1 CA dex
00051B 1 CA dex
00051C 1 CA dex
00051D 1 CA dex
00051E 1 CA dex
00051F 1 CA dex
000520 1 CA dex
000521 1 CA dex
000522 1 CA dex
000523 1 CA dex ;+60
000524 1 CA dex
000525 1 CA dex
000526 1 CA dex
000527 1 CA dex
000528 1 CA dex
000529 1 CA dex
00052A 1 CA dex
00052B 1 CA dex
00052C 1 CA dex
00052D 1 CA dex ;+70
00052E 1 CA dex
00052F 1 CA dex
000530 1 CA dex
000531 1 CA dex
000532 1 CA dex
000533 1 CA dex
000534 1 CA dex
000535 1 CA dex
000536 1 CA dex
000537 1 CA dex ;+80
000538 1 CA dex
000539 1 CA dex
00053A 1 CA dex
00053B 1 CA dex
00053C 1 CA dex
00053D 1 CA dex
00053E 1 CA dex
00053F 1 CA dex
000540 1 CA dex
000541 1 CA dex ;+90
000542 1 CA dex
000543 1 CA dex
000544 1 CA dex
000545 1 CA dex
000546 1 CA dex
000547 1 CA dex
000548 1 CA dex
000549 1 CA dex
00054A 1 CA dex
00054B 1 CA dex ;+100
00054C 1 CA dex
00054D 1 CA dex
00054E 1 CA dex
00054F 1 CA dex
000550 1 CA dex
000551 1 CA dex
000552 1 CA dex
000553 1 CA dex
000554 1 CA dex
000555 1 CA dex ;+110
000556 1 CA dex
000557 1 CA dex
000558 1 CA dex
000559 1 CA dex
00055A 1 CA dex
00055B 1 CA dex
00055C 1 CA dex
00055D 1 CA dex
00055E 1 CA dex
00055F 1 CA dex ;+120
000560 1 CA dex
000561 1 CA dex
000562 1 CA dex
000563 1 CA dex
000564 1 CA dex
000565 1 CA dex
000566 1 EA nop ;offset landing zone - forward branch too far
000567 1 EA nop
000568 1 EA nop
000569 1 EA nop
00056A 1 EA nop
00056B 1 F0 08 beq range_ok ;+127 - max forward
00056D 1 4C 6D 05 trap ; bad range
000570 1 EA nop ;offset landing zone - tolerate +/-5 offset to branch
000571 1 EA nop
000572 1 EA nop
000573 1 EA nop
000574 1 EA nop
000575 1 range_ok:
000575 1 EA nop
000576 1 EA nop
000577 1 EA nop
000578 1 EA nop
000579 1 EA nop
00057A 1 C0 00 cpy #0
00057C 1 F0 03 beq range_end
00057E 1 4C 46 04 jmp range_loop
000581 1 range_end: ;range test successful
000581 1 .endif
000581 1 AD 00 02 C9 next_test
000585 1 01 D0 FE A9
000589 1 02 8D 00 02
00058D 1
00058D 1 ;partial test BNE & CMP, CPX, CPY immediate
00058D 1 C0 01 cpy #1 ;testing BNE true
00058F 1 D0 03 bne test_bne
000591 1 4C 91 05 trap
000594 1 test_bne:
000594 1 A9 00 lda #0
000596 1 C9 00 cmp #0 ;test compare immediate
000598 1 D0 FE trap_ne
00059A 1 90 FE trap_cc
00059C 1 30 FE trap_mi
00059E 1 C9 01 cmp #1
0005A0 1 F0 FE trap_eq
0005A2 1 B0 FE trap_cs
0005A4 1 10 FE trap_pl
0005A6 1 AA tax
0005A7 1 E0 00 cpx #0 ;test compare x immediate
0005A9 1 D0 FE trap_ne
0005AB 1 90 FE trap_cc
0005AD 1 30 FE trap_mi
0005AF 1 E0 01 cpx #1
0005B1 1 F0 FE trap_eq
0005B3 1 B0 FE trap_cs
0005B5 1 10 FE trap_pl
0005B7 1 A8 tay
0005B8 1 C0 00 cpy #0 ;test compare y immediate
0005BA 1 D0 FE trap_ne
0005BC 1 90 FE trap_cc
0005BE 1 30 FE trap_mi
0005C0 1 C0 01 cpy #1
0005C2 1 F0 FE trap_eq
0005C4 1 B0 FE trap_cs
0005C6 1 10 FE trap_pl
0005C8 1 AD 00 02 C9 next_test
0005CC 1 02 D0 FE A9
0005D0 1 03 8D 00 02
0005D4 1 ;testing stack operations PHA PHP PLA PLP
0005D4 1
0005D4 1 A2 FF ldx #$ff ;initialize stack
0005D6 1 9A txs
0005D7 1 A9 55 lda #$55
0005D9 1 48 pha
0005DA 1 A9 AA lda #$aa
0005DC 1 48 pha
0005DD 1 CD FE 01 cmp $1fe ;on stack ?
0005E0 1 D0 FE trap_ne
0005E2 1 BA tsx
0005E3 1 8A txa ;overwrite accu
0005E4 1 C9 FD cmp #$fd ;sp decremented?
0005E6 1 D0 FE trap_ne
0005E8 1 68 pla
0005E9 1 C9 AA cmp #$aa ;successful retreived from stack?
0005EB 1 D0 FE trap_ne
0005ED 1 68 pla
0005EE 1 C9 55 cmp #$55
0005F0 1 D0 FE trap_ne
0005F2 1 CD FF 01 cmp $1ff ;remains on stack?
0005F5 1 D0 FE trap_ne
0005F7 1 BA tsx
0005F8 1 E0 FF cpx #$ff ;sp incremented?
0005FA 1 D0 FE trap_ne
0005FC 1 AD 00 02 C9 next_test
000600 1 03 D0 FE A9
000604 1 04 8D 00 02
000608 1
000608 1 ;testing branch decisions BPL BMI BVC BVS BCC BCS BNE BEQ
000608 1 A9 FF 48 28 set_stat $ff ;all on
00060C 1 10 1A bpl nbr1 ;branches should not be taken
00060E 1 50 1B bvc nbr2
000610 1 90 1C bcc nbr3
000612 1 D0 1D bne nbr4
000614 1 30 03 bmi br1 ;branches should be taken
000616 1 4C 16 06 trap
000619 1 70 03 br1: bvs br2
00061B 1 4C 1B 06 trap
00061E 1 B0 03 br2: bcs br3
000620 1 4C 20 06 trap
000623 1 F0 0F br3: beq br4
000625 1 4C 25 06 trap
000628 1 nbr1:
000628 1 4C 28 06 trap ;previous bpl taken
00062B 1 nbr2:
00062B 1 4C 2B 06 trap ;previous bvc taken
00062E 1 nbr3:
00062E 1 4C 2E 06 trap ;previous bcc taken
000631 1 nbr4:
000631 1 4C 31 06 trap ;previous bne taken
000634 1 08 br4: php
000635 1 BA tsx
000636 1 E0 FE cpx #$fe ;sp after php?
000638 1 D0 FE trap_ne
00063A 1 68 pla
00063B 1 C9 FF cmp_flag $ff ;returned all flags on?
00063D 1 D0 FE trap_ne
00063F 1 BA tsx
000640 1 E0 FF cpx #$ff ;sp after php?
000642 1 D0 FE trap_ne
000644 1 A9 00 48 28 set_stat 0 ;all off
000648 1 30 1A bmi nbr11 ;branches should not be taken
00064A 1 70 1B bvs nbr12
00064C 1 B0 1C bcs nbr13
00064E 1 F0 1D beq nbr14
000650 1 10 03 bpl br11 ;branches should be taken
000652 1 4C 52 06 trap
000655 1 50 03 br11: bvc br12
000657 1 4C 57 06 trap
00065A 1 90 03 br12: bcc br13
00065C 1 4C 5C 06 trap
00065F 1 D0 0F br13: bne br14
000661 1 4C 61 06 trap
000664 1 nbr11:
000664 1 4C 64 06 trap ;previous bmi taken
000667 1 nbr12:
000667 1 4C 67 06 trap ;previous bvs taken
00066A 1 nbr13:
00066A 1 4C 6A 06 trap ;previous bcs taken
00066D 1 nbr14:
00066D 1 4C 6D 06 trap ;previous beq taken
000670 1 08 br14: php
000671 1 68 pla
000672 1 C9 30 cmp_flag 0 ;flags off except break (pushed by sw) + reserved?
000674 1 D0 FE trap_ne
000676 1 ;crosscheck flags
000676 1 A9 02 48 28 set_stat zero
00067A 1 D0 02 bne brzs1
00067C 1 F0 03 beq brzs2
00067E 1 brzs1:
00067E 1 4C 7E 06 trap ;branch zero/non zero
000681 1 B0 02 brzs2: bcs brzs3
000683 1 90 03 bcc brzs4
000685 1 brzs3:
000685 1 4C 85 06 trap ;branch carry/no carry
000688 1 30 02 brzs4: bmi brzs5
00068A 1 10 03 bpl brzs6
00068C 1 brzs5:
00068C 1 4C 8C 06 trap ;branch minus/plus
00068F 1 70 02 brzs6: bvs brzs7
000691 1 50 03 bvc brzs8
000693 1 brzs7:
000693 1 4C 93 06 trap ;branch overflow/no overflow
000696 1 brzs8:
000696 1 A9 01 48 28 set_stat carry
00069A 1 F0 02 beq brcs1
00069C 1 D0 03 bne brcs2
00069E 1 brcs1:
00069E 1 4C 9E 06 trap ;branch zero/non zero
0006A1 1 90 02 brcs2: bcc brcs3
0006A3 1 B0 03 bcs brcs4
0006A5 1 brcs3:
0006A5 1 4C A5 06 trap ;branch carry/no carry
0006A8 1 30 02 brcs4: bmi brcs5
0006AA 1 10 03 bpl brcs6
0006AC 1 brcs5:
0006AC 1 4C AC 06 trap ;branch minus/plus
0006AF 1 70 02 brcs6: bvs brcs7
0006B1 1 50 03 bvc brcs8
0006B3 1 brcs7:
0006B3 1 4C B3 06 trap ;branch overflow/no overflow
0006B6 1
0006B6 1 brcs8:
0006B6 1 A9 80 48 28 set_stat minus
0006BA 1 F0 02 beq brmi1
0006BC 1 D0 03 bne brmi2
0006BE 1 brmi1:
0006BE 1 4C BE 06 trap ;branch zero/non zero
0006C1 1 B0 02 brmi2: bcs brmi3
0006C3 1 90 03 bcc brmi4
0006C5 1 brmi3:
0006C5 1 4C C5 06 trap ;branch carry/no carry
0006C8 1 10 02 brmi4: bpl brmi5
0006CA 1 30 03 bmi brmi6
0006CC 1 brmi5:
0006CC 1 4C CC 06 trap ;branch minus/plus
0006CF 1 70 02 brmi6: bvs brmi7
0006D1 1 50 03 bvc brmi8
0006D3 1 brmi7:
0006D3 1 4C D3 06 trap ;branch overflow/no overflow
0006D6 1 brmi8:
0006D6 1 A9 40 48 28 set_stat overfl
0006DA 1 F0 02 beq brvs1
0006DC 1 D0 03 bne brvs2
0006DE 1 brvs1:
0006DE 1 4C DE 06 trap ;branch zero/non zero
0006E1 1 B0 02 brvs2: bcs brvs3
0006E3 1 90 03 bcc brvs4
0006E5 1 brvs3:
0006E5 1 4C E5 06 trap ;branch carry/no carry
0006E8 1 30 02 brvs4: bmi brvs5
0006EA 1 10 03 bpl brvs6
0006EC 1 brvs5:
0006EC 1 4C EC 06 trap ;branch minus/plus
0006EF 1 50 02 brvs6: bvc brvs7
0006F1 1 70 03 bvs brvs8
0006F3 1 brvs7:
0006F3 1 4C F3 06 trap ;branch overflow/no overflow
0006F6 1 brvs8:
0006F6 1 A9 FD 48 28 set_stat $ff-zero
0006FA 1 F0 02 beq brzc1
0006FC 1 D0 03 bne brzc2
0006FE 1 brzc1:
0006FE 1 4C FE 06 trap ;branch zero/non zero
000701 1 90 02 brzc2: bcc brzc3
000703 1 B0 03 bcs brzc4
000705 1 brzc3:
000705 1 4C 05 07 trap ;branch carry/no carry
000708 1 10 02 brzc4: bpl brzc5
00070A 1 30 03 bmi brzc6
00070C 1 brzc5:
00070C 1 4C 0C 07 trap ;branch minus/plus
00070F 1 50 02 brzc6: bvc brzc7
000711 1 70 03 bvs brzc8
000713 1 brzc7:
000713 1 4C 13 07 trap ;branch overflow/no overflow
000716 1 brzc8:
000716 1 A9 FE 48 28 set_stat $ff-carry
00071A 1 D0 02 bne brcc1
00071C 1 F0 03 beq brcc2
00071E 1 brcc1:
00071E 1 4C 1E 07 trap ;branch zero/non zero
000721 1 B0 02 brcc2: bcs brcc3
000723 1 90 03 bcc brcc4
000725 1 brcc3:
000725 1 4C 25 07 trap ;branch carry/no carry
000728 1 10 02 brcc4: bpl brcc5
00072A 1 30 03 bmi brcc6
00072C 1 brcc5:
00072C 1 4C 2C 07 trap ;branch minus/plus
00072F 1 50 02 brcc6: bvc brcc7
000731 1 70 03 bvs brcc8
000733 1 brcc7:
000733 1 4C 33 07 trap ;branch overflow/no overflow
000736 1 brcc8:
000736 1 A9 7F 48 28 set_stat $ff-minus
00073A 1 D0 02 bne brpl1
00073C 1 F0 03 beq brpl2
00073E 1 brpl1:
00073E 1 4C 3E 07 trap ;branch zero/non zero
000741 1 90 02 brpl2: bcc brpl3
000743 1 B0 03 bcs brpl4
000745 1 brpl3:
000745 1 4C 45 07 trap ;branch carry/no carry
000748 1 30 02 brpl4: bmi brpl5
00074A 1 10 03 bpl brpl6
00074C 1 brpl5:
00074C 1 4C 4C 07 trap ;branch minus/plus
00074F 1 50 02 brpl6: bvc brpl7
000751 1 70 03 bvs brpl8
000753 1 brpl7:
000753 1 4C 53 07 trap ;branch overflow/no overflow
000756 1 brpl8:
000756 1 A9 BF 48 28 set_stat $ff-overfl
00075A 1 D0 02 bne brvc1
00075C 1 F0 03 beq brvc2
00075E 1 brvc1:
00075E 1 4C 5E 07 trap ;branch zero/non zero
000761 1 90 02 brvc2: bcc brvc3
000763 1 B0 03 bcs brvc4
000765 1 brvc3:
000765 1 4C 65 07 trap ;branch carry/no carry
000768 1 10 02 brvc4: bpl brvc5
00076A 1 30 03 bmi brvc6
00076C 1 brvc5:
00076C 1 4C 6C 07 trap ;branch minus/plus
00076F 1 70 02 brvc6: bvs brvc7
000771 1 50 03 bvc brvc8
000773 1 brvc7:
000773 1 4C 73 07 trap ;branch overflow/no overflow
000776 1 brvc8:
000776 1 AD 00 02 C9 next_test
00077A 1 04 D0 FE A9
00077E 1 05 8D 00 02
000782 1
000782 1 ; test PHA does not alter flags or accumulator but PLA does
000782 1 A2 55 ldx #$55 ;x & y protected
000784 1 A0 AA ldy #$aa
000786 1 A9 FF 48 A9 set_a 1,$ff ;push
00078A 1 01 28
00078C 1 48 pha
00078D 1 08 C9 01 D0 tst_a 1,$ff
000791 1 FE 68 48 C9
000795 1 FF D0 FE 28
000799 1 A9 00 48 A9 set_a 0,0
00079D 1 00 28
00079F 1 48 pha
0007A0 1 08 C9 00 D0 tst_a 0,0
0007A4 1 FE 68 48 C9
0007A8 1 30 D0 FE 28
0007AC 1 A9 FF 48 A9 set_a $ff,$ff
0007B0 1 FF 28
0007B2 1 48 pha
0007B3 1 08 C9 FF D0 tst_a $ff,$ff
0007B7 1 FE 68 48 C9
0007BB 1 FF D0 FE 28
0007BF 1 A9 00 48 A9 set_a 1,0
0007C3 1 01 28
0007C5 1 48 pha
0007C6 1 08 C9 01 D0 tst_a 1,0
0007CA 1 FE 68 48 C9
0007CE 1 30 D0 FE 28
0007D2 1 A9 FF 48 A9 set_a 0,$ff
0007D6 1 00 28
0007D8 1 48 pha
0007D9 1 08 C9 00 D0 tst_a 0,$ff
0007DD 1 FE 68 48 C9
0007E1 1 FF D0 FE 28
0007E5 1 A9 00 48 A9 set_a $ff,0
0007E9 1 FF 28
0007EB 1 48 pha
0007EC 1 08 C9 FF D0 tst_a $ff,0
0007F0 1 FE 68 48 C9
0007F4 1 30 D0 FE 28
0007F8 1 A9 FF 48 A9 set_a 0,$ff ;pull
0007FC 1 00 28
0007FE 1 68 pla
0007FF 1 08 C9 FF D0 tst_a $ff,$ff-zero
000803 1 FE 68 48 C9
000807 1 FD D0 FE 28
00080B 1 A9 00 48 A9 set_a $ff,0
00080F 1 FF 28
000811 1 68 pla
000812 1 08 C9 00 D0 tst_a 0,zero
000816 1 FE 68 48 C9
00081A 1 32 D0 FE 28
00081E 1 A9 FF 48 A9 set_a $fe,$ff
000822 1 FE 28
000824 1 68 pla
000825 1 08 C9 01 D0 tst_a 1,$ff-zero-minus
000829 1 FE 68 48 C9
00082D 1 7D D0 FE 28
000831 1 A9 00 48 A9 set_a 0,0
000835 1 00 28
000837 1 68 pla
000838 1 08 C9 FF D0 tst_a $ff,minus
00083C 1 FE 68 48 C9
000840 1 B0 D0 FE 28
000844 1 A9 FF 48 A9 set_a $ff,$ff
000848 1 FF 28
00084A 1 68 pla
00084B 1 08 C9 00 D0 tst_a 0,$ff-minus
00084F 1 FE 68 48 C9
000853 1 7F D0 FE 28
000857 1 A9 00 48 A9 set_a $fe,0
00085B 1 FE 28
00085D 1 68 pla
00085E 1 08 C9 01 D0 tst_a 1,0
000862 1 FE 68 48 C9
000866 1 30 D0 FE 28
00086A 1 E0 55 cpx #$55 ;x & y unchanged?
00086C 1 D0 FE trap_ne
00086E 1 C0 AA cpy #$aa
000870 1 D0 FE trap_ne
000872 1 AD 00 02 C9 next_test
000876 1 05 D0 FE A9
00087A 1 06 8D 00 02
00087E 1
00087E 1 ; partial pretest EOR #
00087E 1 A9 00 48 A9 set_a $3c,0
000882 1 3C 28
000884 1 49 C3 eor #$c3
000886 1 08 C9 FF D0 tst_a $ff,fn
00088A 1 FE 68 48 C9
00088E 1 B0 D0 FE 28
000892 1 A9 00 48 A9 set_a $c3,0
000896 1 C3 28
000898 1 49 C3 eor #$c3
00089A 1 08 C9 00 D0 tst_a 0,fz
00089E 1 FE 68 48 C9
0008A2 1 32 D0 FE 28
0008A6 1 AD 00 02 C9 next_test
0008AA 1 06 D0 FE A9
0008AE 1 07 8D 00 02
0008B2 1
0008B2 1 ; PC modifying instructions except branches (NOP, JMP, JSR, RTS, BRK, RTI)
0008B2 1 ; testing NOP
0008B2 1 A2 24 ldx #$24
0008B4 1 A0 42 ldy #$42
0008B6 1 A9 00 48 A9 set_a $18,0
0008BA 1 18 28
0008BC 1 EA nop
0008BD 1 08 C9 18 D0 tst_a $18,0
0008C1 1 FE 68 48 C9
0008C5 1 30 D0 FE 28
0008C9 1 E0 24 cpx #$24
0008CB 1 D0 FE trap_ne
0008CD 1 C0 42 cpy #$42
0008CF 1 D0 FE trap_ne
0008D1 1 A2 DB ldx #$db
0008D3 1 A0 BD ldy #$bd
0008D5 1 A9 FF 48 A9 set_a $e7,$ff
0008D9 1 E7 28
0008DB 1 EA nop
0008DC 1 08 C9 E7 D0 tst_a $e7,$ff
0008E0 1 FE 68 48 C9
0008E4 1 FF D0 FE 28
0008E8 1 E0 DB cpx #$db
0008EA 1 D0 FE trap_ne
0008EC 1 C0 BD cpy #$bd
0008EE 1 D0 FE trap_ne
0008F0 1 AD 00 02 C9 next_test
0008F4 1 07 D0 FE A9
0008F8 1 08 8D 00 02
0008FC 1
0008FC 1 ; jump absolute
0008FC 1 A9 00 48 28 set_stat $0
000900 1 A9 46 lda #'F'
000902 1 A2 41 ldx #'A'
000904 1 A0 52 ldy #'R' ;N=0, V=0, Z=0, C=0
000906 1 4C EF 36 jmp test_far
000909 1 EA nop
00090A 1 EA nop
00090B 1 D0 FE trap_ne ;runover protection
00090D 1 E8 inx
00090E 1 E8 inx
00090F 1 far_ret:
00090F 1 F0 FE trap_eq ;returned flags OK?
000911 1 10 FE trap_pl
000913 1 90 FE trap_cc
000915 1 50 FE trap_vc
000917 1 C9 EC cmp #('F'^$aa) ;returned registers OK?
000919 1 D0 FE trap_ne
00091B 1 E0 42 cpx #('A'+1)
00091D 1 D0 FE trap_ne
00091F 1 C0 4F cpy #('R'-3)
000921 1 D0 FE trap_ne
000923 1 CA dex
000924 1 C8 iny
000925 1 C8 iny
000926 1 C8 iny
000927 1 49 AA eor #$aa ;N=0, V=1, Z=0, C=1
000929 1 4C 32 09 jmp test_near
00092C 1 EA nop
00092D 1 EA nop
00092E 1 D0 FE trap_ne ;runover protection
000930 1 E8 inx
000931 1 E8 inx
000932 1 test_near:
000932 1 F0 FE trap_eq ;passed flags OK?
000934 1 30 FE trap_mi
000936 1 90 FE trap_cc
000938 1 50 FE trap_vc
00093A 1 C9 46 cmp #'F' ;passed registers OK?
00093C 1 D0 FE trap_ne
00093E 1 E0 41 cpx #'A'
000940 1 D0 FE trap_ne
000942 1 C0 52 cpy #'R'
000944 1 D0 FE trap_ne
000946 1 AD 00 02 C9 next_test
00094A 1 08 D0 FE A9
00094E 1 09 8D 00 02
000952 1
000952 1 ; jump indirect
000952 1 A9 00 48 28 set_stat 0
000956 1 A9 49 lda #'I'
000958 1 A2 4E ldx #'N'
00095A 1 A0 44 ldy #'D' ;N=0, V=0, Z=0, C=0
00095C 1 6C 1E 37 jmp (ptr_tst_ind)
00095F 1 EA nop
000960 1 D0 FE trap_ne ;runover protection
000962 1 88 dey
000963 1 88 dey
000964 1 ind_ret:
000964 1 08 php ;either SP or Y count will fail, if we do not hit
000965 1 88 dey
000966 1 88 dey
000967 1 88 dey
000968 1 28 plp
000969 1 F0 FE trap_eq ;returned flags OK?
00096B 1 10 FE trap_pl
00096D 1 90 FE trap_cc
00096F 1 50 FE trap_vc
000971 1 C9 E3 cmp #('I'^$aa) ;returned registers OK?
000973 1 D0 FE trap_ne
000975 1 E0 4F cpx #('N'+1)
000977 1 D0 FE trap_ne
000979 1 C0 3E cpy #('D'-6)
00097B 1 D0 FE trap_ne
00097D 1 BA tsx ;SP check
00097E 1 E0 FF cpx #$ff
000980 1 D0 FE trap_ne
000982 1 AD 00 02 C9 next_test
000986 1 09 D0 FE A9
00098A 1 0A 8D 00 02
00098E 1
00098E 1 ; jump subroutine & return from subroutine
00098E 1 A9 00 48 28 set_stat 0
000992 1 A9 4A lda #'J'
000994 1 A2 53 ldx #'S'
000996 1 A0 52 ldy #'R' ;N=0, V=0, Z=0, C=0
000998 1 20 5D 37 jsr test_jsr
00099B 1 jsr_ret = *-1 ;last address of jsr = return address
00099B 1 08 php ;either SP or Y count will fail, if we do not hit
00099C 1 88 dey
00099D 1 88 dey
00099E 1 88 dey
00099F 1 28 plp
0009A0 1 F0 FE trap_eq ;returned flags OK?
0009A2 1 10 FE trap_pl
0009A4 1 90 FE trap_cc
0009A6 1 50 FE trap_vc
0009A8 1 C9 E0 cmp #('J'^$aa) ;returned registers OK?
0009AA 1 D0 FE trap_ne
0009AC 1 E0 54 cpx #('S'+1)
0009AE 1 D0 FE trap_ne
0009B0 1 C0 4C cpy #('R'-6)
0009B2 1 D0 FE trap_ne
0009B4 1 BA tsx ;sp?
0009B5 1 E0 FF cpx #$ff
0009B7 1 D0 FE trap_ne
0009B9 1 AD 00 02 C9 next_test
0009BD 1 0A D0 FE A9
0009C1 1 0B 8D 00 02
0009C5 1
0009C5 1 ; break & return from interrupt
0009C5 1 .if ROM_vectors = 1
0009C5 1 A9 00 load_flag 0 ;with interrupts enabled if allowed!
0009C7 1 48 pha
0009C8 1 A9 42 lda #'B'
0009CA 1 A2 52 ldx #'R'
0009CC 1 A0 4B ldy #'K'
0009CE 1 28 plp ;N=0, V=0, Z=0, C=0
0009CF 1 00 brk
0009D0 1 .else
0009D0 1 lda #>brk_ret0 ;emulated break
0009D0 1 pha
0009D0 1 lda #<brk_ret0
0009D0 1 pha
0009D0 1 load_flag fao ;set break & unused on stack
0009D0 1 pha
0009D0 1 load_flag intdis ;during interrupt
0009D0 1 pha
0009D0 1 lda #'B'
0009D0 1 ldx #'R'
0009D0 1 ldy #'K'
0009D0 1 plp ;N=0, V=0, Z=0, C=0
0009D0 1 jmp irq_trap
0009D0 1 .endif
0009D0 1 88 dey ;should not be executed
0009D1 1 brk_ret0: ;address of break return
0009D1 1 08 php ;either SP or Y count will fail, if we do not hit
0009D2 1 88 dey
0009D3 1 88 dey
0009D4 1 88 dey
0009D5 1 C9 E8 cmp #'B'^$aa ;returned registers OK?
0009D7 1 ;the IRQ vector was never executed if A & X stay unmodified
0009D7 1 D0 FE trap_ne
0009D9 1 E0 53 cpx #'R'+1
0009DB 1 D0 FE trap_ne
0009DD 1 C0 45 cpy #'K'-6
0009DF 1 D0 FE trap_ne
0009E1 1 68 pla ;returned flags OK (unchanged)?
0009E2 1 C9 30 cmp_flag 0
0009E4 1 D0 FE trap_ne
0009E6 1 BA tsx ;sp?
0009E7 1 E0 FF cpx #$ff
0009E9 1 D0 FE trap_ne
0009EB 1 .if ROM_vectors = 1
0009EB 1 A9 FF load_flag $ff ;with interrupts disabled if allowed!
0009ED 1 48 pha
0009EE 1 A9 BD lda #$ff-'B'
0009F0 1 A2 AD ldx #$ff-'R'
0009F2 1 A0 B4 ldy #$ff-'K'
0009F4 1 28 plp ;N=1, V=1, Z=1, C=1
0009F5 1 00 brk
0009F6 1 .else
0009F6 1 lda #>brk_ret1 ;emulated break
0009F6 1 pha
0009F6 1 lda #<brk_ret1
0009F6 1 pha
0009F6 1 load_flag $ff
0009F6 1 pha ;set break & unused on stack
0009F6 1 pha ;actual flags
0009F6 1 lda #$ff-'B'
0009F6 1 ldx #$ff-'R'
0009F6 1 ldy #$ff-'K'
0009F6 1 plp ;N=1, V=1, Z=1, C=1
0009F6 1 jmp irq_trap
0009F6 1 .endif
0009F6 1 88 dey ;should not be executed
0009F7 1 brk_ret1: ;address of break return
0009F7 1 08 php ;either SP or Y count will fail, if we do not hit
0009F8 1 88 dey
0009F9 1 88 dey
0009FA 1 88 dey
0009FB 1 C9 17 cmp #($ff-'B')^$aa ;returned registers OK?
0009FD 1 ;the IRQ vector was never executed if A & X stay unmodified
0009FD 1 D0 FE trap_ne
0009FF 1 E0 AE cpx #$ff-'R'+1
000A01 1 D0 FE trap_ne
000A03 1 C0 AE cpy #$ff-'K'-6
000A05 1 D0 FE trap_ne
000A07 1 68 pla ;returned flags OK (unchanged)?
000A08 1 C9 FF cmp_flag $ff
000A0A 1 D0 FE trap_ne
000A0C 1 BA tsx ;sp?
000A0D 1 E0 FF cpx #$ff
000A0F 1 D0 FE trap_ne
000A11 1 AD 00 02 C9 next_test
000A15 1 0B D0 FE A9
000A19 1 0C 8D 00 02
000A1D 1
000A1D 1 ; test set and clear flags CLC CLI CLD CLV SEC SEI SED
000A1D 1 A9 FF 48 28 set_stat $ff
000A21 1 18 clc
000A22 1 08 68 48 C9 tst_stat $ff-carry
000A26 1 FE D0 FE 28
000A2A 1 38 sec
000A2B 1 08 68 48 C9 tst_stat $ff
000A2F 1 FF D0 FE 28
000A33 1 .if I_flag = 3
000A33 1 58 cli
000A34 1 08 68 48 C9 tst_stat $ff-intdis
000A38 1 FB D0 FE 28
000A3C 1 78 sei
000A3D 1 08 68 48 C9 tst_stat $ff
000A41 1 FF D0 FE 28
000A45 1 .endif
000A45 1 D8 cld
000A46 1 08 68 48 C9 tst_stat $ff-decmode
000A4A 1 F7 D0 FE 28
000A4E 1 F8 sed
000A4F 1 08 68 48 C9 tst_stat $ff
000A53 1 FF D0 FE 28
000A57 1 B8 clv
000A58 1 08 68 48 C9 tst_stat $ff-overfl
000A5C 1 BF D0 FE 28
000A60 1 A9 00 48 28 set_stat 0
000A64 1 08 68 48 C9 tst_stat 0
000A68 1 30 D0 FE 28
000A6C 1 38 sec
000A6D 1 08 68 48 C9 tst_stat carry
000A71 1 31 D0 FE 28
000A75 1 18 clc
000A76 1 08 68 48 C9 tst_stat 0
000A7A 1 30 D0 FE 28
000A7E 1 .if I_flag = 3
000A7E 1 78 sei
000A7F 1 08 68 48 C9 tst_stat intdis
000A83 1 34 D0 FE 28
000A87 1 58 cli
000A88 1 08 68 48 C9 tst_stat 0
000A8C 1 30 D0 FE 28
000A90 1 .endif
000A90 1 F8 sed
000A91 1 08 68 48 C9 tst_stat decmode
000A95 1 38 D0 FE 28
000A99 1 D8 cld
000A9A 1 08 68 48 C9 tst_stat 0
000A9E 1 30 D0 FE 28
000AA2 1 A9 40 48 28 set_stat overfl
000AA6 1 08 68 48 C9 tst_stat overfl
000AAA 1 70 D0 FE 28
000AAE 1 B8 clv
000AAF 1 08 68 48 C9 tst_stat 0
000AB3 1 30 D0 FE 28
000AB7 1 AD 00 02 C9 next_test
000ABB 1 0C D0 FE A9
000ABF 1 0D 8D 00 02
000AC3 1 ; testing index register increment/decrement and transfer
000AC3 1 ; INX INY DEX DEY TAX TXA TAY TYA
000AC3 1 A2 FE ldx #$fe
000AC5 1 A9 FF 48 28 set_stat $ff
000AC9 1 E8 inx ;ff
000ACA 1 08 E0 FF D0 tst_x $ff,$ff-zero
000ACE 1 FE 68 48 C9
000AD2 1 FD D0 FE 28
000AD6 1 E8 inx ;00
000AD7 1 08 E0 00 D0 tst_x 0,$ff-minus
000ADB 1 FE 68 48 C9
000ADF 1 7F D0 FE 28
000AE3 1 E8 inx ;01
000AE4 1 08 E0 01 D0 tst_x 1,$ff-minus-zero
000AE8 1 FE 68 48 C9
000AEC 1 7D D0 FE 28
000AF0 1 CA dex ;00
000AF1 1 08 E0 00 D0 tst_x 0,$ff-minus
000AF5 1 FE 68 48 C9
000AF9 1 7F D0 FE 28
000AFD 1 CA dex ;ff
000AFE 1 08 E0 FF D0 tst_x $ff,$ff-zero
000B02 1 FE 68 48 C9
000B06 1 FD D0 FE 28
000B0A 1 CA dex ;fe
000B0B 1 A9 00 48 28 set_stat 0
000B0F 1 E8 inx ;ff
000B10 1 08 E0 FF D0 tst_x $ff,minus
000B14 1 FE 68 48 C9
000B18 1 B0 D0 FE 28
000B1C 1 E8 inx ;00
000B1D 1 08 E0 00 D0 tst_x 0,zero
000B21 1 FE 68 48 C9
000B25 1 32 D0 FE 28
000B29 1 E8 inx ;01
000B2A 1 08 E0 01 D0 tst_x 1,0
000B2E 1 FE 68 48 C9
000B32 1 30 D0 FE 28
000B36 1 CA dex ;00
000B37 1 08 E0 00 D0 tst_x 0,zero
000B3B 1 FE 68 48 C9
000B3F 1 32 D0 FE 28
000B43 1 CA dex ;ff
000B44 1 08 E0 FF D0 tst_x $ff,minus
000B48 1 FE 68 48 C9
000B4C 1 B0 D0 FE 28
000B50 1
000B50 1 A0 FE ldy #$fe
000B52 1 A9 FF 48 28 set_stat $ff
000B56 1 C8 iny ;ff
000B57 1 08 C0 FF D0 tst_y $ff,$ff-zero
000B5B 1 FE 68 48 C9
000B5F 1 FD D0 FE 28
000B63 1 C8 iny ;00
000B64 1 08 C0 00 D0 tst_y 0,$ff-minus
000B68 1 FE 68 48 C9
000B6C 1 7F D0 FE 28
000B70 1 C8 iny ;01
000B71 1 08 C0 01 D0 tst_y 1,$ff-minus-zero
000B75 1 FE 68 48 C9
000B79 1 7D D0 FE 28
000B7D 1 88 dey ;00
000B7E 1 08 C0 00 D0 tst_y 0,$ff-minus
000B82 1 FE 68 48 C9
000B86 1 7F D0 FE 28
000B8A 1 88 dey ;ff
000B8B 1 08 C0 FF D0 tst_y $ff,$ff-zero
000B8F 1 FE 68 48 C9
000B93 1 FD D0 FE 28
000B97 1 88 dey ;fe
000B98 1 A9 00 48 28 set_stat 0
000B9C 1 C8 iny ;ff
000B9D 1 08 C0 FF D0 tst_y $ff,0+minus
000BA1 1 FE 68 48 C9
000BA5 1 B0 D0 FE 28
000BA9 1 C8 iny ;00
000BAA 1 08 C0 00 D0 tst_y 0,zero
000BAE 1 FE 68 48 C9
000BB2 1 32 D0 FE 28
000BB6 1 C8 iny ;01
000BB7 1 08 C0 01 D0 tst_y 1,0
000BBB 1 FE 68 48 C9
000BBF 1 30 D0 FE 28
000BC3 1 88 dey ;00
000BC4 1 08 C0 00 D0 tst_y 0,zero
000BC8 1 FE 68 48 C9
000BCC 1 32 D0 FE 28
000BD0 1 88 dey ;ff
000BD1 1 08 C0 FF D0 tst_y $ff,minus
000BD5 1 FE 68 48 C9
000BD9 1 B0 D0 FE 28
000BDD 1
000BDD 1 A2 FF ldx #$ff
000BDF 1 A9 FF 48 28 set_stat $ff
000BE3 1 8A txa
000BE4 1 08 C9 FF D0 tst_a $ff,$ff-zero
000BE8 1 FE 68 48 C9
000BEC 1 FD D0 FE 28
000BF0 1 08 php
000BF1 1 E8 inx ;00
000BF2 1 28 plp
000BF3 1 8A txa
000BF4 1 08 C9 00 D0 tst_a 0,$ff-minus
000BF8 1 FE 68 48 C9
000BFC 1 7F D0 FE 28
000C00 1 08 php
000C01 1 E8 inx ;01
000C02 1 28 plp
000C03 1 8A txa
000C04 1 08 C9 01 D0 tst_a 1,$ff-minus-zero
000C08 1 FE 68 48 C9
000C0C 1 7D D0 FE 28
000C10 1 A9 00 48 28 set_stat 0
000C14 1 8A txa
000C15 1 08 C9 01 D0 tst_a 1,0
000C19 1 FE 68 48 C9
000C1D 1 30 D0 FE 28
000C21 1 08 php
000C22 1 CA dex ;00
000C23 1 28 plp
000C24 1 8A txa
000C25 1 08 C9 00 D0 tst_a 0,zero
000C29 1 FE 68 48 C9
000C2D 1 32 D0 FE 28
000C31 1 08 php
000C32 1 CA dex ;ff
000C33 1 28 plp
000C34 1 8A txa
000C35 1 08 C9 FF D0 tst_a $ff,minus
000C39 1 FE 68 48 C9
000C3D 1 B0 D0 FE 28
000C41 1
000C41 1 A0 FF ldy #$ff
000C43 1 A9 FF 48 28 set_stat $ff
000C47 1 98 tya
000C48 1 08 C9 FF D0 tst_a $ff,$ff-zero
000C4C 1 FE 68 48 C9
000C50 1 FD D0 FE 28
000C54 1 08 php
000C55 1 C8 iny ;00
000C56 1 28 plp
000C57 1 98 tya
000C58 1 08 C9 00 D0 tst_a 0,$ff-minus
000C5C 1 FE 68 48 C9
000C60 1 7F D0 FE 28
000C64 1 08 php
000C65 1 C8 iny ;01
000C66 1 28 plp
000C67 1 98 tya
000C68 1 08 C9 01 D0 tst_a 1,$ff-minus-zero
000C6C 1 FE 68 48 C9
000C70 1 7D D0 FE 28
000C74 1 A9 00 48 28 set_stat 0
000C78 1 98 tya
000C79 1 08 C9 01 D0 tst_a 1,0
000C7D 1 FE 68 48 C9
000C81 1 30 D0 FE 28
000C85 1 08 php
000C86 1 88 dey ;00
000C87 1 28 plp
000C88 1 98 tya
000C89 1 08 C9 00 D0 tst_a 0,zero
000C8D 1 FE 68 48 C9
000C91 1 32 D0 FE 28
000C95 1 08 php
000C96 1 88 dey ;ff
000C97 1 28 plp
000C98 1 98 tya
000C99 1 08 C9 FF D0 tst_a $ff,minus
000C9D 1 FE 68 48 C9
000CA1 1 B0 D0 FE 28
000CA5 1
000CA5 1 A9 FF load_flag $ff
000CA7 1 48 pha
000CA8 1 A2 FF ldx #$ff ;ff
000CAA 1 8A txa
000CAB 1 28 plp
000CAC 1 A8 tay
000CAD 1 08 C0 FF D0 tst_y $ff,$ff-zero
000CB1 1 FE 68 48 C9
000CB5 1 FD D0 FE 28
000CB9 1 08 php
000CBA 1 E8 inx ;00
000CBB 1 8A txa
000CBC 1 28 plp
000CBD 1 A8 tay
000CBE 1 08 C0 00 D0 tst_y 0,$ff-minus
000CC2 1 FE 68 48 C9
000CC6 1 7F D0 FE 28
000CCA 1 08 php
000CCB 1 E8 inx ;01
000CCC 1 8A txa
000CCD 1 28 plp
000CCE 1 A8 tay
000CCF 1 08 C0 01 D0 tst_y 1,$ff-minus-zero
000CD3 1 FE 68 48 C9
000CD7 1 7D D0 FE 28
000CDB 1 A9 00 load_flag 0
000CDD 1 48 pha
000CDE 1 A9 00 lda #0
000CE0 1 8A txa
000CE1 1 28 plp
000CE2 1 A8 tay
000CE3 1 08 C0 01 D0 tst_y 1,0
000CE7 1 FE 68 48 C9
000CEB 1 30 D0 FE 28
000CEF 1 08 php
000CF0 1 CA dex ;00
000CF1 1 8A txa
000CF2 1 28 plp
000CF3 1 A8 tay
000CF4 1 08 C0 00 D0 tst_y 0,zero
000CF8 1 FE 68 48 C9
000CFC 1 32 D0 FE 28
000D00 1 08 php
000D01 1 CA dex ;ff
000D02 1 8A txa
000D03 1 28 plp
000D04 1 A8 tay
000D05 1 08 C0 FF D0 tst_y $ff,minus
000D09 1 FE 68 48 C9
000D0D 1 B0 D0 FE 28
000D11 1
000D11 1
000D11 1 A9 FF load_flag $ff
000D13 1 48 pha
000D14 1 A0 FF ldy #$ff ;ff
000D16 1 98 tya
000D17 1 28 plp
000D18 1 AA tax
000D19 1 08 E0 FF D0 tst_x $ff,$ff-zero
000D1D 1 FE 68 48 C9
000D21 1 FD D0 FE 28
000D25 1 08 php
000D26 1 C8 iny ;00
000D27 1 98 tya
000D28 1 28 plp
000D29 1 AA tax
000D2A 1 08 E0 00 D0 tst_x 0,$ff-minus
000D2E 1 FE 68 48 C9
000D32 1 7F D0 FE 28
000D36 1 08 php
000D37 1 C8 iny ;01
000D38 1 98 tya
000D39 1 28 plp
000D3A 1 AA tax
000D3B 1 08 E0 01 D0 tst_x 1,$ff-minus-zero
000D3F 1 FE 68 48 C9
000D43 1 7D D0 FE 28
000D47 1 A9 00 load_flag 0
000D49 1 48 pha
000D4A 1 A9 00 lda #0 ;preset status
000D4C 1 98 tya
000D4D 1 28 plp
000D4E 1 AA tax
000D4F 1 08 E0 01 D0 tst_x 1,0
000D53 1 FE 68 48 C9
000D57 1 30 D0 FE 28
000D5B 1 08 php
000D5C 1 88 dey ;00
000D5D 1 98 tya
000D5E 1 28 plp
000D5F 1 AA tax
000D60 1 08 E0 00 D0 tst_x 0,zero
000D64 1 FE 68 48 C9
000D68 1 32 D0 FE 28
000D6C 1 08 php
000D6D 1 88 dey ;ff
000D6E 1 98 tya
000D6F 1 28 plp
000D70 1 AA tax
000D71 1 08 E0 FF D0 tst_x $ff,minus
000D75 1 FE 68 48 C9
000D79 1 B0 D0 FE 28
000D7D 1 AD 00 02 C9 next_test
000D81 1 0D D0 FE A9
000D85 1 0E 8D 00 02
000D89 1
000D89 1 ;TSX sets NZ - TXS does not
000D89 1 ; This section also tests for proper stack wrap around.
000D89 1 A2 01 ldx #1 ;01
000D8B 1 A9 FF 48 28 set_stat $ff
000D8F 1 9A txs
000D90 1 08 php
000D91 1 AD 01 01 lda $101
000D94 1 C9 FF cmp_flag $ff
000D96 1 D0 FE trap_ne
000D98 1 A9 00 48 28 set_stat 0
000D9C 1 9A txs
000D9D 1 08 php
000D9E 1 AD 01 01 lda $101
000DA1 1 C9 30 cmp_flag 0
000DA3 1 D0 FE trap_ne
000DA5 1 CA dex ;00
000DA6 1 A9 FF 48 28 set_stat $ff
000DAA 1 9A txs
000DAB 1 08 php
000DAC 1 AD 00 01 lda $100
000DAF 1 C9 FF cmp_flag $ff
000DB1 1 D0 FE trap_ne
000DB3 1 A9 00 48 28 set_stat 0
000DB7 1 9A txs
000DB8 1 08 php
000DB9 1 AD 00 01 lda $100
000DBC 1 C9 30 cmp_flag 0
000DBE 1 D0 FE trap_ne
000DC0 1 CA dex ;ff
000DC1 1 A9 FF 48 28 set_stat $ff
000DC5 1 9A txs
000DC6 1 08 php
000DC7 1 AD FF 01 lda $1ff
000DCA 1 C9 FF cmp_flag $ff
000DCC 1 D0 FE trap_ne
000DCE 1 A9 00 48 28 set_stat 0
000DD2 1 9A txs
000DD3 1 08 php
000DD4 1 AD FF 01 lda $1ff
000DD7 1 C9 30 cmp_flag 0
000DD9 1
000DD9 1 A2 01 ldx #1
000DDB 1 9A txs ;sp=01
000DDC 1 A9 FF 48 28 set_stat $ff
000DE0 1 BA tsx ;clears Z, N
000DE1 1 08 php ;sp=00
000DE2 1 E0 01 cpx #1
000DE4 1 D0 FE trap_ne
000DE6 1 AD 01 01 lda $101
000DE9 1 C9 7D cmp_flag $ff-minus-zero
000DEB 1 D0 FE trap_ne
000DED 1 A9 FF 48 28 set_stat $ff
000DF1 1 BA tsx ;clears N, sets Z
000DF2 1 08 php ;sp=ff
000DF3 1 E0 00 cpx #0
000DF5 1 D0 FE trap_ne
000DF7 1 AD 00 01 lda $100
000DFA 1 C9 7F cmp_flag $ff-minus
000DFC 1 D0 FE trap_ne
000DFE 1 A9 FF 48 28 set_stat $ff
000E02 1 BA tsx ;clears N, sets Z
000E03 1 08 php ;sp=fe
000E04 1 E0 FF cpx #$ff
000E06 1 D0 FE trap_ne
000E08 1 AD FF 01 lda $1ff
000E0B 1 C9 FD cmp_flag $ff-zero
000E0D 1 D0 FE trap_ne
000E0F 1
000E0F 1 A2 01 ldx #1
000E11 1 9A txs ;sp=01
000E12 1 A9 00 48 28 set_stat 0
000E16 1 BA tsx ;clears Z, N
000E17 1 08 php ;sp=00
000E18 1 E0 01 cpx #1
000E1A 1 D0 FE trap_ne
000E1C 1 AD 01 01 lda $101
000E1F 1 C9 30 cmp_flag 0
000E21 1 D0 FE trap_ne
000E23 1 A9 00 48 28 set_stat 0
000E27 1 BA tsx ;clears N, sets Z
000E28 1 08 php ;sp=ff
000E29 1 E0 00 cpx #0
000E2B 1 D0 FE trap_ne
000E2D 1 AD 00 01 lda $100
000E30 1 C9 32 cmp_flag zero
000E32 1 D0 FE trap_ne
000E34 1 A9 00 48 28 set_stat 0
000E38 1 BA tsx ;clears N, sets Z
000E39 1 08 php ;sp=fe
000E3A 1 E0 FF cpx #$ff
000E3C 1 D0 FE trap_ne
000E3E 1 AD FF 01 lda $1ff
000E41 1 C9 B0 cmp_flag minus
000E43 1 D0 FE trap_ne
000E45 1 68 pla ;sp=ff
000E46 1 AD 00 02 C9 next_test
000E4A 1 0E D0 FE A9
000E4E 1 0F 8D 00 02
000E52 1
000E52 1 ; testing index register load & store LDY LDX STY STX all addressing modes
000E52 1 ; LDX / STX - zp,y / abs,y
000E52 1 A0 03 ldy #3
000E54 1 tldx:
000E54 1 A9 00 48 28 set_stat 0
000E58 1 B6 15 ldx zp1,y
000E5A 1 08 php ;test stores do not alter flags
000E5B 1 8A txa
000E5C 1 49 C3 eor #$c3
000E5E 1 28 plp
000E5F 1 99 03 02 sta abst,y
000E62 1 08 php ;flags after load/store sequence
000E63 1 49 C3 eor #$c3
000E65 1 D9 18 02 cmp abs1,y ;test result
000E68 1 D0 FE trap_ne
000E6A 1 68 pla ;load status
000E6B 1 49 30 eor_flag 0
000E6D 1 D9 1D 02 cmp fLDx,y ;test flags
000E70 1 D0 FE trap_ne
000E72 1 88 dey
000E73 1 10 DF bpl tldx
000E75 1
000E75 1 A0 03 ldy #3
000E77 1 tldx1:
000E77 1 A9 FF 48 28 set_stat $ff
000E7B 1 B6 15 ldx zp1,y
000E7D 1 08 php ;test stores do not alter flags
000E7E 1 8A txa
000E7F 1 49 C3 eor #$c3
000E81 1 28 plp
000E82 1 99 03 02 sta abst,y
000E85 1 08 php ;flags after load/store sequence
000E86 1 49 C3 eor #$c3
000E88 1 D9 18 02 cmp abs1,y ;test result
000E8B 1 D0 FE trap_ne
000E8D 1 68 pla ;load status
000E8E 1 49 7D eor_flag <~fnz ;mask bits not altered
000E90 1 D9 1D 02 cmp fLDx,y ;test flags
000E93 1 D0 FE trap_ne
000E95 1 88 dey
000E96 1 10 DF bpl tldx1
000E98 1
000E98 1 A0 03 ldy #3
000E9A 1 tldx2:
000E9A 1 A9 00 48 28 set_stat 0
000E9E 1 BE 18 02 ldx abs1,y
000EA1 1 08 php ;test stores do not alter flags
000EA2 1 8A txa
000EA3 1 49 C3 eor #$c3
000EA5 1 AA tax
000EA6 1 28 plp
000EA7 1 96 0C stx zpt,y
000EA9 1 08 php ;flags after load/store sequence
000EAA 1 49 C3 eor #$c3
000EAC 1 D9 15 00 cmp zp1,y ;test result
000EAF 1 D0 FE trap_ne
000EB1 1 68 pla ;load status
000EB2 1 49 30 eor_flag 0
000EB4 1 D9 1D 02 cmp fLDx,y ;test flags
000EB7 1 D0 FE trap_ne
000EB9 1 88 dey
000EBA 1 10 DE bpl tldx2
000EBC 1
000EBC 1 A0 03 ldy #3
000EBE 1 tldx3:
000EBE 1 A9 FF 48 28 set_stat $ff
000EC2 1 BE 18 02 ldx abs1,y
000EC5 1 08 php ;test stores do not alter flags
000EC6 1 8A txa
000EC7 1 49 C3 eor #$c3
000EC9 1 AA tax
000ECA 1 28 plp
000ECB 1 96 0C stx zpt,y
000ECD 1 08 php ;flags after load/store sequence
000ECE 1 49 C3 eor #$c3
000ED0 1 D9 15 00 cmp zp1,y ;test result
000ED3 1 D0 FE trap_ne
000ED5 1 68 pla ;load status
000ED6 1 49 7D eor_flag <~fnz ;mask bits not altered
000ED8 1 D9 1D 02 cmp fLDx,y ;test flags
000EDB 1 D0 FE trap_ne
000EDD 1 88 dey
000EDE 1 10 DE bpl tldx3
000EE0 1
000EE0 1 A0 03 ldy #3 ;testing store result
000EE2 1 A2 00 ldx #0
000EE4 1 B9 0C 00 tstx: lda zpt,y
000EE7 1 49 C3 eor #$c3
000EE9 1 D9 15 00 cmp zp1,y
000EEC 1 D0 FE trap_ne ;store to zp data
000EEE 1 96 0C stx zpt,y ;clear
000EF0 1 B9 03 02 lda abst,y
000EF3 1 49 C3 eor #$c3
000EF5 1 D9 18 02 cmp abs1,y
000EF8 1 D0 FE trap_ne ;store to abs data
000EFA 1 8A txa
000EFB 1 99 03 02 sta abst,y ;clear
000EFE 1 88 dey
000EFF 1 10 E3 bpl tstx
000F01 1 AD 00 02 C9 next_test
000F05 1 0F D0 FE A9
000F09 1 10 8D 00 02
000F0D 1
000F0D 1 ; indexed wraparound test (only zp should wrap)
000F0D 1 A0 FD ldy #3+$fa
000F0F 1 B6 1B tldx4: ldx <(zp1-$fa),y ;wrap on indexed zp
000F11 1 8A txa
000F12 1 99 09 01 sta abst-$fa,y ;no STX abs,y!
000F15 1 88 dey
000F16 1 C0 FA cpy #$fa
000F18 1 B0 F5 bcs tldx4
000F1A 1 A0 FD ldy #3+$fa
000F1C 1 BE 1E 01 tldx5: ldx abs1-$fa,y ;no wrap on indexed abs
000F1F 1 96 12 stx <(zpt-$fa),y
000F21 1 88 dey
000F22 1 C0 FA cpy #$fa
000F24 1 B0 F6 bcs tldx5
000F26 1 A0 03 ldy #3 ;testing wraparound result
000F28 1 A2 00 ldx #0
000F2A 1 B9 0C 00 tstx1: lda zpt,y
000F2D 1 D9 15 00 cmp zp1,y
000F30 1 D0 FE trap_ne ;store to zp data
000F32 1 96 0C stx zpt,y ;clear
000F34 1 B9 03 02 lda abst,y
000F37 1 D9 18 02 cmp abs1,y
000F3A 1 D0 FE trap_ne ;store to abs data
000F3C 1 8A txa
000F3D 1 99 03 02 sta abst,y ;clear
000F40 1 88 dey
000F41 1 10 E7 bpl tstx1
000F43 1 AD 00 02 C9 next_test
000F47 1 10 D0 FE A9
000F4B 1 11 8D 00 02
000F4F 1
000F4F 1 ; LDY / STY - zp,x / abs,x
000F4F 1 A2 03 ldx #3
000F51 1 tldy:
000F51 1 A9 00 48 28 set_stat 0
000F55 1 B4 15 ldy zp1,x
000F57 1 08 php ;test stores do not alter flags
000F58 1 98 tya
000F59 1 49 C3 eor #$c3
000F5B 1 28 plp
000F5C 1 9D 03 02 sta abst,x
000F5F 1 08 php ;flags after load/store sequence
000F60 1 49 C3 eor #$c3
000F62 1 DD 18 02 cmp abs1,x ;test result
000F65 1 D0 FE trap_ne
000F67 1 68 pla ;load status
000F68 1 49 30 eor_flag 0
000F6A 1 DD 1D 02 cmp fLDx,x ;test flags
000F6D 1 D0 FE trap_ne
000F6F 1 CA dex
000F70 1 10 DF bpl tldy
000F72 1
000F72 1 A2 03 ldx #3
000F74 1 tldy1:
000F74 1 A9 FF 48 28 set_stat $ff
000F78 1 B4 15 ldy zp1,x
000F7A 1 08 php ;test stores do not alter flags
000F7B 1 98 tya
000F7C 1 49 C3 eor #$c3
000F7E 1 28 plp
000F7F 1 9D 03 02 sta abst,x
000F82 1 08 php ;flags after load/store sequence
000F83 1 49 C3 eor #$c3
000F85 1 DD 18 02 cmp abs1,x ;test result
000F88 1 D0 FE trap_ne
000F8A 1 68 pla ;load status
000F8B 1 49 7D eor_flag <~fnz ;mask bits not altered
000F8D 1 DD 1D 02 cmp fLDx,x ;test flags
000F90 1 D0 FE trap_ne
000F92 1 CA dex
000F93 1 10 DF bpl tldy1
000F95 1
000F95 1 A2 03 ldx #3
000F97 1 tldy2:
000F97 1 A9 00 48 28 set_stat 0
000F9B 1 BC 18 02 ldy abs1,x
000F9E 1 08 php ;test stores do not alter flags
000F9F 1 98 tya
000FA0 1 49 C3 eor #$c3
000FA2 1 A8 tay
000FA3 1 28 plp
000FA4 1 94 0C sty zpt,x
000FA6 1 08 php ;flags after load/store sequence
000FA7 1 49 C3 eor #$c3
000FA9 1 D5 15 cmp zp1,x ;test result
000FAB 1 D0 FE trap_ne
000FAD 1 68 pla ;load status
000FAE 1 49 30 eor_flag 0
000FB0 1 DD 1D 02 cmp fLDx,x ;test flags
000FB3 1 D0 FE trap_ne
000FB5 1 CA dex
000FB6 1 10 DF bpl tldy2
000FB8 1
000FB8 1 A2 03 ldx #3
000FBA 1 tldy3:
000FBA 1 A9 FF 48 28 set_stat $ff
000FBE 1 BC 18 02 ldy abs1,x
000FC1 1 08 php ;test stores do not alter flags
000FC2 1 98 tya
000FC3 1 49 C3 eor #$c3
000FC5 1 A8 tay
000FC6 1 28 plp
000FC7 1 94 0C sty zpt,x
000FC9 1 08 php ;flags after load/store sequence
000FCA 1 49 C3 eor #$c3
000FCC 1 D5 15 cmp zp1,x ;test result
000FCE 1 D0 FE trap_ne
000FD0 1 68 pla ;load status
000FD1 1 49 7D eor_flag <~fnz ;mask bits not altered
000FD3 1 DD 1D 02 cmp fLDx,x ;test flags
000FD6 1 D0 FE trap_ne
000FD8 1 CA dex
000FD9 1 10 DF bpl tldy3
000FDB 1
000FDB 1 A2 03 ldx #3 ;testing store result
000FDD 1 A0 00 ldy #0
000FDF 1 B5 0C tsty: lda zpt,x
000FE1 1 49 C3 eor #$c3
000FE3 1 D5 15 cmp zp1,x
000FE5 1 D0 FE trap_ne ;store to zp,x data
000FE7 1 94 0C sty zpt,x ;clear
000FE9 1 BD 03 02 lda abst,x
000FEC 1 49 C3 eor #$c3
000FEE 1 DD 18 02 cmp abs1,x
000FF1 1 D0 FE trap_ne ;store to abs,x data
000FF3 1 8A txa
000FF4 1 9D 03 02 sta abst,x ;clear
000FF7 1 CA dex
000FF8 1 10 E5 bpl tsty
000FFA 1 AD 00 02 C9 next_test
000FFE 1 11 D0 FE A9
001002 1 12 8D 00 02
001006 1
001006 1 ; indexed wraparound test (only zp should wrap)
001006 1 A2 FD ldx #3+$fa
001008 1 B4 1B tldy4: ldy <(zp1-$fa),x ;wrap on indexed zp
00100A 1 98 tya
00100B 1 9D 09 01 sta abst-$fa,x ;no STX abs,x!
00100E 1 CA dex
00100F 1 E0 FA cpx #$fa
001011 1 B0 F5 bcs tldy4
001013 1 A2 FD ldx #3+$fa
001015 1 BC 1E 01 tldy5: ldy abs1-$fa,x ;no wrap on indexed abs
001018 1 94 12 sty <(zpt-$fa),x
00101A 1 CA dex
00101B 1 E0 FA cpx #$fa
00101D 1 B0 F6 bcs tldy5
00101F 1 A2 03 ldx #3 ;testing wraparound result
001021 1 A0 00 ldy #0
001023 1 B5 0C tsty1: lda zpt,x
001025 1 D5 15 cmp zp1,x
001027 1 D0 FE trap_ne ;store to zp,x data
001029 1 94 0C sty zpt,x ;clear
00102B 1 BD 03 02 lda abst,x
00102E 1 DD 18 02 cmp abs1,x
001031 1 D0 FE trap_ne ;store to abs,x data
001033 1 8A txa
001034 1 9D 03 02 sta abst,x ;clear
001037 1 CA dex
001038 1 10 E9 bpl tsty1
00103A 1 AD 00 02 C9 next_test
00103E 1 12 D0 FE A9
001042 1 13 8D 00 02
001046 1
001046 1 ; LDX / STX - zp / abs / #
001046 1 A9 00 48 28 set_stat 0
00104A 1 A6 15 ldx zp1
00104C 1 08 php ;test stores do not alter flags
00104D 1 8A txa
00104E 1 49 C3 eor #$c3
001050 1 AA tax
001051 1 28 plp
001052 1 8E 03 02 stx abst
001055 1 08 php ;flags after load/store sequence
001056 1 49 C3 eor #$c3
001058 1 AA tax
001059 1 E0 C3 cpx #$c3 ;test result
00105B 1 D0 FE trap_ne
00105D 1 68 pla ;load status
00105E 1 49 30 eor_flag 0
001060 1 CD 1D 02 cmp fLDx ;test flags
001063 1 D0 FE trap_ne
001065 1 A9 00 48 28 set_stat 0
001069 1 A6 16 ldx zp1+1
00106B 1 08 php ;test stores do not alter flags
00106C 1 8A txa
00106D 1 49 C3 eor #$c3
00106F 1 AA tax
001070 1 28 plp
001071 1 8E 04 02 stx abst+1
001074 1 08 php ;flags after load/store sequence
001075 1 49 C3 eor #$c3
001077 1 AA tax
001078 1 E0 82 cpx #$82 ;test result
00107A 1 D0 FE trap_ne
00107C 1 68 pla ;load status
00107D 1 49 30 eor_flag 0
00107F 1 CD 1E 02 cmp fLDx+1 ;test flags
001082 1 D0 FE trap_ne
001084 1 A9 00 48 28 set_stat 0
001088 1 A6 17 ldx zp1+2
00108A 1 08 php ;test stores do not alter flags
00108B 1 8A txa
00108C 1 49 C3 eor #$c3
00108E 1 AA tax
00108F 1 28 plp
001090 1 8E 05 02 stx abst+2
001093 1 08 php ;flags after load/store sequence
001094 1 49 C3 eor #$c3
001096 1 AA tax
001097 1 E0 41 cpx #$41 ;test result
001099 1 D0 FE trap_ne
00109B 1 68 pla ;load status
00109C 1 49 30 eor_flag 0
00109E 1 CD 1F 02 cmp fLDx+2 ;test flags
0010A1 1 D0 FE trap_ne
0010A3 1 A9 00 48 28 set_stat 0
0010A7 1 A6 18 ldx zp1+3
0010A9 1 08 php ;test stores do not alter flags
0010AA 1 8A txa
0010AB 1 49 C3 eor #$c3
0010AD 1 AA tax
0010AE 1 28 plp
0010AF 1 8E 06 02 stx abst+3
0010B2 1 08 php ;flags after load/store sequence
0010B3 1 49 C3 eor #$c3
0010B5 1 AA tax
0010B6 1 E0 00 cpx #0 ;test result
0010B8 1 D0 FE trap_ne
0010BA 1 68 pla ;load status
0010BB 1 49 30 eor_flag 0
0010BD 1 CD 20 02 cmp fLDx+3 ;test flags
0010C0 1 D0 FE trap_ne
0010C2 1
0010C2 1 A9 FF 48 28 set_stat $ff
0010C6 1 A6 15 ldx zp1
0010C8 1 08 php ;test stores do not alter flags
0010C9 1 8A txa
0010CA 1 49 C3 eor #$c3
0010CC 1 AA tax
0010CD 1 28 plp
0010CE 1 8E 03 02 stx abst
0010D1 1 08 php ;flags after load/store sequence
0010D2 1 49 C3 eor #$c3
0010D4 1 AA tax
0010D5 1 E0 C3 cpx #$c3 ;test result
0010D7 1 D0 FE trap_ne ;
0010D9 1 68 pla ;load status
0010DA 1 49 7D eor_flag <~fnz ;mask bits not altered
0010DC 1 CD 1D 02 cmp fLDx ;test flags
0010DF 1 D0 FE trap_ne
0010E1 1 A9 FF 48 28 set_stat $ff
0010E5 1 A6 16 ldx zp1+1
0010E7 1 08 php ;test stores do not alter flags
0010E8 1 8A txa
0010E9 1 49 C3 eor #$c3
0010EB 1 AA tax
0010EC 1 28 plp
0010ED 1 8E 04 02 stx abst+1
0010F0 1 08 php ;flags after load/store sequence
0010F1 1 49 C3 eor #$c3
0010F3 1 AA tax
0010F4 1 E0 82 cpx #$82 ;test result
0010F6 1 D0 FE trap_ne
0010F8 1 68 pla ;load status
0010F9 1 49 7D eor_flag <~fnz ;mask bits not altered
0010FB 1 CD 1E 02 cmp fLDx+1 ;test flags
0010FE 1 D0 FE trap_ne
001100 1 A9 FF 48 28 set_stat $ff
001104 1 A6 17 ldx zp1+2
001106 1 08 php ;test stores do not alter flags
001107 1 8A txa
001108 1 49 C3 eor #$c3
00110A 1 AA tax
00110B 1 28 plp
00110C 1 8E 05 02 stx abst+2
00110F 1 08 php ;flags after load/store sequence
001110 1 49 C3 eor #$c3
001112 1 AA tax
001113 1 E0 41 cpx #$41 ;test result
001115 1 D0 FE trap_ne ;
001117 1 68 pla ;load status
001118 1 49 7D eor_flag <~fnz ;mask bits not altered
00111A 1 CD 1F 02 cmp fLDx+2 ;test flags
00111D 1 D0 FE trap_ne
00111F 1 A9 FF 48 28 set_stat $ff
001123 1 A6 18 ldx zp1+3
001125 1 08 php ;test stores do not alter flags
001126 1 8A txa
001127 1 49 C3 eor #$c3
001129 1 AA tax
00112A 1 28 plp
00112B 1 8E 06 02 stx abst+3
00112E 1 08 php ;flags after load/store sequence
00112F 1 49 C3 eor #$c3
001131 1 AA tax
001132 1 E0 00 cpx #0 ;test result
001134 1 D0 FE trap_ne
001136 1 68 pla ;load status
001137 1 49 7D eor_flag <~fnz ;mask bits not altered
001139 1 CD 20 02 cmp fLDx+3 ;test flags
00113C 1 D0 FE trap_ne
00113E 1
00113E 1 A9 00 48 28 set_stat 0
001142 1 AE 18 02 ldx abs1
001145 1 08 php ;test stores do not alter flags
001146 1 8A txa
001147 1 49 C3 eor #$c3
001149 1 AA tax
00114A 1 28 plp
00114B 1 86 0C stx zpt
00114D 1 08 php ;flags after load/store sequence
00114E 1 49 C3 eor #$c3
001150 1 C5 15 cmp zp1 ;test result
001152 1 D0 FE trap_ne
001154 1 68 pla ;load status
001155 1 49 30 eor_flag 0
001157 1 CD 1D 02 cmp fLDx ;test flags
00115A 1 D0 FE trap_ne
00115C 1 A9 00 48 28 set_stat 0
001160 1 AE 19 02 ldx abs1+1
001163 1 08 php ;test stores do not alter flags
001164 1 8A txa
001165 1 49 C3 eor #$c3
001167 1 AA tax
001168 1 28 plp
001169 1 86 0D stx zpt+1
00116B 1 08 php ;flags after load/store sequence
00116C 1 49 C3 eor #$c3
00116E 1 C5 16 cmp zp1+1 ;test result
001170 1 D0 FE trap_ne
001172 1 68 pla ;load status
001173 1 49 30 eor_flag 0
001175 1 CD 1E 02 cmp fLDx+1 ;test flags
001178 1 D0 FE trap_ne
00117A 1 A9 00 48 28 set_stat 0
00117E 1 AE 1A 02 ldx abs1+2
001181 1 08 php ;test stores do not alter flags
001182 1 8A txa
001183 1 49 C3 eor #$c3
001185 1 AA tax
001186 1 28 plp
001187 1 86 0E stx zpt+2
001189 1 08 php ;flags after load/store sequence
00118A 1 49 C3 eor #$c3
00118C 1 C5 17 cmp zp1+2 ;test result
00118E 1 D0 FE trap_ne
001190 1 68 pla ;load status
001191 1 49 30 eor_flag 0
001193 1 CD 1F 02 cmp fLDx+2 ;test flags
001196 1 D0 FE trap_ne
001198 1 A9 00 48 28 set_stat 0
00119C 1 AE 1B 02 ldx abs1+3
00119F 1 08 php ;test stores do not alter flags
0011A0 1 8A txa
0011A1 1 49 C3 eor #$c3
0011A3 1 AA tax
0011A4 1 28 plp
0011A5 1 86 0F stx zpt+3
0011A7 1 08 php ;flags after load/store sequence
0011A8 1 49 C3 eor #$c3
0011AA 1 C5 18 cmp zp1+3 ;test result
0011AC 1 D0 FE trap_ne
0011AE 1 68 pla ;load status
0011AF 1 49 30 eor_flag 0
0011B1 1 CD 20 02 cmp fLDx+3 ;test flags
0011B4 1 D0 FE trap_ne
0011B6 1
0011B6 1 A9 FF 48 28 set_stat $ff
0011BA 1 AE 18 02 ldx abs1
0011BD 1 08 php ;test stores do not alter flags
0011BE 1 8A txa
0011BF 1 49 C3 eor #$c3
0011C1 1 AA tax
0011C2 1 28 plp
0011C3 1 86 0C stx zpt
0011C5 1 08 php ;flags after load/store sequence
0011C6 1 49 C3 eor #$c3
0011C8 1 AA tax
0011C9 1 E4 15 cpx zp1 ;test result
0011CB 1 D0 FE trap_ne
0011CD 1 68 pla ;load status
0011CE 1 49 7D eor_flag <~fnz ;mask bits not altered
0011D0 1 CD 1D 02 cmp fLDx ;test flags
0011D3 1 D0 FE trap_ne
0011D5 1 A9 FF 48 28 set_stat $ff
0011D9 1 AE 19 02 ldx abs1+1
0011DC 1 08 php ;test stores do not alter flags
0011DD 1 8A txa
0011DE 1 49 C3 eor #$c3
0011E0 1 AA tax
0011E1 1 28 plp
0011E2 1 86 0D stx zpt+1
0011E4 1 08 php ;flags after load/store sequence
0011E5 1 49 C3 eor #$c3
0011E7 1 AA tax
0011E8 1 E4 16 cpx zp1+1 ;test result
0011EA 1 D0 FE trap_ne
0011EC 1 68 pla ;load status
0011ED 1 49 7D eor_flag <~fnz ;mask bits not altered
0011EF 1 CD 1E 02 cmp fLDx+1 ;test flags
0011F2 1 D0 FE trap_ne
0011F4 1 A9 FF 48 28 set_stat $ff
0011F8 1 AE 1A 02 ldx abs1+2
0011FB 1 08 php ;test stores do not alter flags
0011FC 1 8A txa
0011FD 1 49 C3 eor #$c3
0011FF 1 AA tax
001200 1 28 plp
001201 1 86 0E stx zpt+2
001203 1 08 php ;flags after load/store sequence
001204 1 49 C3 eor #$c3
001206 1 AA tax
001207 1 E4 17 cpx zp1+2 ;test result
001209 1 D0 FE trap_ne
00120B 1 68 pla ;load status
00120C 1 49 7D eor_flag <~fnz ;mask bits not altered
00120E 1 CD 1F 02 cmp fLDx+2 ;test flags
001211 1 D0 FE trap_ne
001213 1 A9 FF 48 28 set_stat $ff
001217 1 AE 1B 02 ldx abs1+3
00121A 1 08 php ;test stores do not alter flags
00121B 1 8A txa
00121C 1 49 C3 eor #$c3
00121E 1 AA tax
00121F 1 28 plp
001220 1 86 0F stx zpt+3
001222 1 08 php ;flags after load/store sequence
001223 1 49 C3 eor #$c3
001225 1 AA tax
001226 1 E4 18 cpx zp1+3 ;test result
001228 1 D0 FE trap_ne
00122A 1 68 pla ;load status
00122B 1 49 7D eor_flag <~fnz ;mask bits not altered
00122D 1 CD 20 02 cmp fLDx+3 ;test flags
001230 1 D0 FE trap_ne
001232 1
001232 1 A9 00 48 28 set_stat 0
001236 1 A2 C3 ldx #$c3
001238 1 08 php
001239 1 EC 18 02 cpx abs1 ;test result
00123C 1 D0 FE trap_ne
00123E 1 68 pla ;load status
00123F 1 49 30 eor_flag 0
001241 1 CD 1D 02 cmp fLDx ;test flags
001244 1 D0 FE trap_ne
001246 1 A9 00 48 28 set_stat 0
00124A 1 A2 82 ldx #$82
00124C 1 08 php
00124D 1 EC 19 02 cpx abs1+1 ;test result
001250 1 D0 FE trap_ne
001252 1 68 pla ;load status
001253 1 49 30 eor_flag 0
001255 1 CD 1E 02 cmp fLDx+1 ;test flags
001258 1 D0 FE trap_ne
00125A 1 A9 00 48 28 set_stat 0
00125E 1 A2 41 ldx #$41
001260 1 08 php
001261 1 EC 1A 02 cpx abs1+2 ;test result
001264 1 D0 FE trap_ne
001266 1 68 pla ;load status
001267 1 49 30 eor_flag 0
001269 1 CD 1F 02 cmp fLDx+2 ;test flags
00126C 1 D0 FE trap_ne
00126E 1 A9 00 48 28 set_stat 0
001272 1 A2 00 ldx #0
001274 1 08 php
001275 1 EC 1B 02 cpx abs1+3 ;test result
001278 1 D0 FE trap_ne
00127A 1 68 pla ;load status
00127B 1 49 30 eor_flag 0
00127D 1 CD 20 02 cmp fLDx+3 ;test flags
001280 1 D0 FE trap_ne
001282 1
001282 1 A9 FF 48 28 set_stat $ff
001286 1 A2 C3 ldx #$c3
001288 1 08 php
001289 1 EC 18 02 cpx abs1 ;test result
00128C 1 D0 FE trap_ne
00128E 1 68 pla ;load status
00128F 1 49 7D eor_flag <~fnz ;mask bits not altered
001291 1 CD 1D 02 cmp fLDx ;test flags
001294 1 D0 FE trap_ne
001296 1 A9 FF 48 28 set_stat $ff
00129A 1 A2 82 ldx #$82
00129C 1 08 php
00129D 1 EC 19 02 cpx abs1+1 ;test result
0012A0 1 D0 FE trap_ne
0012A2 1 68 pla ;load status
0012A3 1 49 7D eor_flag <~fnz ;mask bits not altered
0012A5 1 CD 1E 02 cmp fLDx+1 ;test flags
0012A8 1 D0 FE trap_ne
0012AA 1 A9 FF 48 28 set_stat $ff
0012AE 1 A2 41 ldx #$41
0012B0 1 08 php
0012B1 1 EC 1A 02 cpx abs1+2 ;test result
0012B4 1 D0 FE trap_ne
0012B6 1 68 pla ;load status
0012B7 1 49 7D eor_flag <~fnz ;mask bits not altered
0012B9 1 CD 1F 02 cmp fLDx+2 ;test flags
0012BC 1 D0 FE trap_ne
0012BE 1 A9 FF 48 28 set_stat $ff
0012C2 1 A2 00 ldx #0
0012C4 1 08 php
0012C5 1 EC 1B 02 cpx abs1+3 ;test result
0012C8 1 D0 FE trap_ne
0012CA 1 68 pla ;load status
0012CB 1 49 7D eor_flag <~fnz ;mask bits not altered
0012CD 1 CD 20 02 cmp fLDx+3 ;test flags
0012D0 1 D0 FE trap_ne
0012D2 1
0012D2 1 A2 00 ldx #0
0012D4 1 A5 0C lda zpt
0012D6 1 49 C3 eor #$c3
0012D8 1 C5 15 cmp zp1
0012DA 1 D0 FE trap_ne ;store to zp data
0012DC 1 86 0C stx zpt ;clear
0012DE 1 AD 03 02 lda abst
0012E1 1 49 C3 eor #$c3
0012E3 1 CD 18 02 cmp abs1
0012E6 1 D0 FE trap_ne ;store to abs data
0012E8 1 8E 03 02 stx abst ;clear
0012EB 1 A5 0D lda zpt+1
0012ED 1 49 C3 eor #$c3
0012EF 1 C5 16 cmp zp1+1
0012F1 1 D0 FE trap_ne ;store to zp data
0012F3 1 86 0D stx zpt+1 ;clear
0012F5 1 AD 04 02 lda abst+1
0012F8 1 49 C3 eor #$c3
0012FA 1 CD 19 02 cmp abs1+1
0012FD 1 D0 FE trap_ne ;store to abs data
0012FF 1 8E 04 02 stx abst+1 ;clear
001302 1 A5 0E lda zpt+2
001304 1 49 C3 eor #$c3
001306 1 C5 17 cmp zp1+2
001308 1 D0 FE trap_ne ;store to zp data
00130A 1 86 0E stx zpt+2 ;clear
00130C 1 AD 05 02 lda abst+2
00130F 1 49 C3 eor #$c3
001311 1 CD 1A 02 cmp abs1+2
001314 1 D0 FE trap_ne ;store to abs data
001316 1 8E 05 02 stx abst+2 ;clear
001319 1 A5 0F lda zpt+3
00131B 1 49 C3 eor #$c3
00131D 1 C5 18 cmp zp1+3
00131F 1 D0 FE trap_ne ;store to zp data
001321 1 86 0F stx zpt+3 ;clear
001323 1 AD 06 02 lda abst+3
001326 1 49 C3 eor #$c3
001328 1 CD 1B 02 cmp abs1+3
00132B 1 D0 FE trap_ne ;store to abs data
00132D 1 8E 06 02 stx abst+3 ;clear
001330 1 AD 00 02 C9 next_test
001334 1 13 D0 FE A9
001338 1 14 8D 00 02
00133C 1
00133C 1 ; LDY / STY - zp / abs / #
00133C 1 A9 00 48 28 set_stat 0
001340 1 A4 15 ldy zp1
001342 1 08 php ;test stores do not alter flags
001343 1 98 tya
001344 1 49 C3 eor #$c3
001346 1 A8 tay
001347 1 28 plp
001348 1 8C 03 02 sty abst
00134B 1 08 php ;flags after load/store sequence
00134C 1 49 C3 eor #$c3
00134E 1 A8 tay
00134F 1 C0 C3 cpy #$c3 ;test result
001351 1 D0 FE trap_ne
001353 1 68 pla ;load status
001354 1 49 30 eor_flag 0
001356 1 CD 1D 02 cmp fLDx ;test flags
001359 1 D0 FE trap_ne
00135B 1 A9 00 48 28 set_stat 0
00135F 1 A4 16 ldy zp1+1
001361 1 08 php ;test stores do not alter flags
001362 1 98 tya
001363 1 49 C3 eor #$c3
001365 1 A8 tay
001366 1 28 plp
001367 1 8C 04 02 sty abst+1
00136A 1 08 php ;flags after load/store sequence
00136B 1 49 C3 eor #$c3
00136D 1 A8 tay
00136E 1 C0 82 cpy #$82 ;test result
001370 1 D0 FE trap_ne
001372 1 68 pla ;load status
001373 1 49 30 eor_flag 0
001375 1 CD 1E 02 cmp fLDx+1 ;test flags
001378 1 D0 FE trap_ne
00137A 1 A9 00 48 28 set_stat 0
00137E 1 A4 17 ldy zp1+2
001380 1 08 php ;test stores do not alter flags
001381 1 98 tya
001382 1 49 C3 eor #$c3
001384 1 A8 tay
001385 1 28 plp
001386 1 8C 05 02 sty abst+2
001389 1 08 php ;flags after load/store sequence
00138A 1 49 C3 eor #$c3
00138C 1 A8 tay
00138D 1 C0 41 cpy #$41 ;test result
00138F 1 D0 FE trap_ne
001391 1 68 pla ;load status
001392 1 49 30 eor_flag 0
001394 1 CD 1F 02 cmp fLDx+2 ;test flags
001397 1 D0 FE trap_ne
001399 1 A9 00 48 28 set_stat 0
00139D 1 A4 18 ldy zp1+3
00139F 1 08 php ;test stores do not alter flags
0013A0 1 98 tya
0013A1 1 49 C3 eor #$c3
0013A3 1 A8 tay
0013A4 1 28 plp
0013A5 1 8C 06 02 sty abst+3
0013A8 1 08 php ;flags after load/store sequence
0013A9 1 49 C3 eor #$c3
0013AB 1 A8 tay
0013AC 1 C0 00 cpy #0 ;test result
0013AE 1 D0 FE trap_ne
0013B0 1 68 pla ;load status
0013B1 1 49 30 eor_flag 0
0013B3 1 CD 20 02 cmp fLDx+3 ;test flags
0013B6 1 D0 FE trap_ne
0013B8 1
0013B8 1 A9 FF 48 28 set_stat $ff
0013BC 1 A4 15 ldy zp1
0013BE 1 08 php ;test stores do not alter flags
0013BF 1 98 tya
0013C0 1 49 C3 eor #$c3
0013C2 1 A8 tay
0013C3 1 28 plp
0013C4 1 8C 03 02 sty abst
0013C7 1 08 php ;flags after load/store sequence
0013C8 1 49 C3 eor #$c3
0013CA 1 A8 tay
0013CB 1 C0 C3 cpy #$c3 ;test result
0013CD 1 D0 FE trap_ne
0013CF 1 68 pla ;load status
0013D0 1 49 7D eor_flag <~fnz ;mask bits not altered
0013D2 1 CD 1D 02 cmp fLDx ;test flags
0013D5 1 D0 FE trap_ne
0013D7 1 A9 FF 48 28 set_stat $ff
0013DB 1 A4 16 ldy zp1+1
0013DD 1 08 php ;test stores do not alter flags
0013DE 1 98 tya
0013DF 1 49 C3 eor #$c3
0013E1 1 A8 tay
0013E2 1 28 plp
0013E3 1 8C 04 02 sty abst+1
0013E6 1 08 php ;flags after load/store sequence
0013E7 1 49 C3 eor #$c3
0013E9 1 A8 tay
0013EA 1 C0 82 cpy #$82 ;test result
0013EC 1 D0 FE trap_ne
0013EE 1 68 pla ;load status
0013EF 1 49 7D eor_flag <~fnz ;mask bits not altered
0013F1 1 CD 1E 02 cmp fLDx+1 ;test flags
0013F4 1 D0 FE trap_ne
0013F6 1 A9 FF 48 28 set_stat $ff
0013FA 1 A4 17 ldy zp1+2
0013FC 1 08 php ;test stores do not alter flags
0013FD 1 98 tya
0013FE 1 49 C3 eor #$c3
001400 1 A8 tay
001401 1 28 plp
001402 1 8C 05 02 sty abst+2
001405 1 08 php ;flags after load/store sequence
001406 1 49 C3 eor #$c3
001408 1 A8 tay
001409 1 C0 41 cpy #$41 ;test result
00140B 1 D0 FE trap_ne
00140D 1 68 pla ;load status
00140E 1 49 7D eor_flag <~fnz ;mask bits not altered
001410 1 CD 1F 02 cmp fLDx+2 ;test flags
001413 1 D0 FE trap_ne
001415 1 A9 FF 48 28 set_stat $ff
001419 1 A4 18 ldy zp1+3
00141B 1 08 php ;test stores do not alter flags
00141C 1 98 tya
00141D 1 49 C3 eor #$c3
00141F 1 A8 tay
001420 1 28 plp
001421 1 8C 06 02 sty abst+3
001424 1 08 php ;flags after load/store sequence
001425 1 49 C3 eor #$c3
001427 1 A8 tay
001428 1 C0 00 cpy #0 ;test result
00142A 1 D0 FE trap_ne
00142C 1 68 pla ;load status
00142D 1 49 7D eor_flag <~fnz ;mask bits not altered
00142F 1 CD 20 02 cmp fLDx+3 ;test flags
001432 1 D0 FE trap_ne
001434 1
001434 1 A9 00 48 28 set_stat 0
001438 1 AC 18 02 ldy abs1
00143B 1 08 php ;test stores do not alter flags
00143C 1 98 tya
00143D 1 49 C3 eor #$c3
00143F 1 A8 tay
001440 1 28 plp
001441 1 84 0C sty zpt
001443 1 08 php ;flags after load/store sequence
001444 1 49 C3 eor #$c3
001446 1 A8 tay
001447 1 C4 15 cpy zp1 ;test result
001449 1 D0 FE trap_ne
00144B 1 68 pla ;load status
00144C 1 49 30 eor_flag 0
00144E 1 CD 1D 02 cmp fLDx ;test flags
001451 1 D0 FE trap_ne
001453 1 A9 00 48 28 set_stat 0
001457 1 AC 19 02 ldy abs1+1
00145A 1 08 php ;test stores do not alter flags
00145B 1 98 tya
00145C 1 49 C3 eor #$c3
00145E 1 A8 tay
00145F 1 28 plp
001460 1 84 0D sty zpt+1
001462 1 08 php ;flags after load/store sequence
001463 1 49 C3 eor #$c3
001465 1 A8 tay
001466 1 C4 16 cpy zp1+1 ;test result
001468 1 D0 FE trap_ne
00146A 1 68 pla ;load status
00146B 1 49 30 eor_flag 0
00146D 1 CD 1E 02 cmp fLDx+1 ;test flags
001470 1 D0 FE trap_ne
001472 1 A9 00 48 28 set_stat 0
001476 1 AC 1A 02 ldy abs1+2
001479 1 08 php ;test stores do not alter flags
00147A 1 98 tya
00147B 1 49 C3 eor #$c3
00147D 1 A8 tay
00147E 1 28 plp
00147F 1 84 0E sty zpt+2
001481 1 08 php ;flags after load/store sequence
001482 1 49 C3 eor #$c3
001484 1 A8 tay
001485 1 C4 17 cpy zp1+2 ;test result
001487 1 D0 FE trap_ne
001489 1 68 pla ;load status
00148A 1 49 30 eor_flag 0
00148C 1 CD 1F 02 cmp fLDx+2 ;test flags
00148F 1 D0 FE trap_ne
001491 1 A9 00 48 28 set_stat 0
001495 1 AC 1B 02 ldy abs1+3
001498 1 08 php ;test stores do not alter flags
001499 1 98 tya
00149A 1 49 C3 eor #$c3
00149C 1 A8 tay
00149D 1 28 plp
00149E 1 84 0F sty zpt+3
0014A0 1 08 php ;flags after load/store sequence
0014A1 1 49 C3 eor #$c3
0014A3 1 A8 tay
0014A4 1 C4 18 cpy zp1+3 ;test result
0014A6 1 D0 FE trap_ne
0014A8 1 68 pla ;load status
0014A9 1 49 30 eor_flag 0
0014AB 1 CD 20 02 cmp fLDx+3 ;test flags
0014AE 1 D0 FE trap_ne
0014B0 1
0014B0 1 A9 FF 48 28 set_stat $ff
0014B4 1 AC 18 02 ldy abs1
0014B7 1 08 php ;test stores do not alter flags
0014B8 1 98 tya
0014B9 1 49 C3 eor #$c3
0014BB 1 A8 tay
0014BC 1 28 plp
0014BD 1 84 0C sty zpt
0014BF 1 08 php ;flags after load/store sequence
0014C0 1 49 C3 eor #$c3
0014C2 1 A8 tay
0014C3 1 C5 15 cmp zp1 ;test result
0014C5 1 D0 FE trap_ne
0014C7 1 68 pla ;load status
0014C8 1 49 7D eor_flag <~fnz ;mask bits not altered
0014CA 1 CD 1D 02 cmp fLDx ;test flags
0014CD 1 D0 FE trap_ne
0014CF 1 A9 FF 48 28 set_stat $ff
0014D3 1 AC 19 02 ldy abs1+1
0014D6 1 08 php ;test stores do not alter flags
0014D7 1 98 tya
0014D8 1 49 C3 eor #$c3
0014DA 1 A8 tay
0014DB 1 28 plp
0014DC 1 84 0D sty zpt+1
0014DE 1 08 php ;flags after load/store sequence
0014DF 1 49 C3 eor #$c3
0014E1 1 A8 tay
0014E2 1 C5 16 cmp zp1+1 ;test result
0014E4 1 D0 FE trap_ne
0014E6 1 68 pla ;load status
0014E7 1 49 7D eor_flag <~fnz ;mask bits not altered
0014E9 1 CD 1E 02 cmp fLDx+1 ;test flags
0014EC 1 D0 FE trap_ne
0014EE 1 A9 FF 48 28 set_stat $ff
0014F2 1 AC 1A 02 ldy abs1+2
0014F5 1 08 php ;test stores do not alter flags
0014F6 1 98 tya
0014F7 1 49 C3 eor #$c3
0014F9 1 A8 tay
0014FA 1 28 plp
0014FB 1 84 0E sty zpt+2
0014FD 1 08 php ;flags after load/store sequence
0014FE 1 49 C3 eor #$c3
001500 1 A8 tay
001501 1 C5 17 cmp zp1+2 ;test result
001503 1 D0 FE trap_ne
001505 1 68 pla ;load status
001506 1 49 7D eor_flag <~fnz ;mask bits not altered
001508 1 CD 1F 02 cmp fLDx+2 ;test flags
00150B 1 D0 FE trap_ne
00150D 1 A9 FF 48 28 set_stat $ff
001511 1 AC 1B 02 ldy abs1+3
001514 1 08 php ;test stores do not alter flags
001515 1 98 tya
001516 1 49 C3 eor #$c3
001518 1 A8 tay
001519 1 28 plp
00151A 1 84 0F sty zpt+3
00151C 1 08 php ;flags after load/store sequence
00151D 1 49 C3 eor #$c3
00151F 1 A8 tay
001520 1 C5 18 cmp zp1+3 ;test result
001522 1 D0 FE trap_ne
001524 1 68 pla ;load status
001525 1 49 7D eor_flag <~fnz ;mask bits not altered
001527 1 CD 20 02 cmp fLDx+3 ;test flags
00152A 1 D0 FE trap_ne
00152C 1
00152C 1
00152C 1 A9 00 48 28 set_stat 0
001530 1 A0 C3 ldy #$c3
001532 1 08 php
001533 1 CC 18 02 cpy abs1 ;test result
001536 1 D0 FE trap_ne
001538 1 68 pla ;load status
001539 1 49 30 eor_flag 0
00153B 1 CD 1D 02 cmp fLDx ;test flags
00153E 1 D0 FE trap_ne
001540 1 A9 00 48 28 set_stat 0
001544 1 A0 82 ldy #$82
001546 1 08 php
001547 1 CC 19 02 cpy abs1+1 ;test result
00154A 1 D0 FE trap_ne
00154C 1 68 pla ;load status
00154D 1 49 30 eor_flag 0
00154F 1 CD 1E 02 cmp fLDx+1 ;test flags
001552 1 D0 FE trap_ne
001554 1 A9 00 48 28 set_stat 0
001558 1 A0 41 ldy #$41
00155A 1 08 php
00155B 1 CC 1A 02 cpy abs1+2 ;test result
00155E 1 D0 FE trap_ne
001560 1 68 pla ;load status
001561 1 49 30 eor_flag 0
001563 1 CD 1F 02 cmp fLDx+2 ;test flags
001566 1 D0 FE trap_ne
001568 1 A9 00 48 28 set_stat 0
00156C 1 A0 00 ldy #0
00156E 1 08 php
00156F 1 CC 1B 02 cpy abs1+3 ;test result
001572 1 D0 FE trap_ne
001574 1 68 pla ;load status
001575 1 49 30 eor_flag 0
001577 1 CD 20 02 cmp fLDx+3 ;test flags
00157A 1 D0 FE trap_ne
00157C 1
00157C 1 A9 FF 48 28 set_stat $ff
001580 1 A0 C3 ldy #$c3
001582 1 08 php
001583 1 CC 18 02 cpy abs1 ;test result
001586 1 D0 FE trap_ne
001588 1 68 pla ;load status
001589 1 49 7D eor_flag <~fnz ;mask bits not altered
00158B 1 CD 1D 02 cmp fLDx ;test flags
00158E 1 D0 FE trap_ne
001590 1 A9 FF 48 28 set_stat $ff
001594 1 A0 82 ldy #$82
001596 1 08 php
001597 1 CC 19 02 cpy abs1+1 ;test result
00159A 1 D0 FE trap_ne
00159C 1 68 pla ;load status
00159D 1 49 7D eor_flag <~fnz ;mask bits not altered
00159F 1 CD 1E 02 cmp fLDx+1 ;test flags
0015A2 1 D0 FE trap_ne
0015A4 1 A9 FF 48 28 set_stat $ff
0015A8 1 A0 41 ldy #$41
0015AA 1 08 php
0015AB 1 CC 1A 02 cpy abs1+2 ;test result
0015AE 1 D0 FE trap_ne
0015B0 1 68 pla ;load status
0015B1 1 49 7D eor_flag <~fnz ;mask bits not altered
0015B3 1 CD 1F 02 cmp fLDx+2 ;test flags
0015B6 1 D0 FE trap_ne
0015B8 1 A9 FF 48 28 set_stat $ff
0015BC 1 A0 00 ldy #0
0015BE 1 08 php
0015BF 1 CC 1B 02 cpy abs1+3 ;test result
0015C2 1 D0 FE trap_ne
0015C4 1 68 pla ;load status
0015C5 1 49 7D eor_flag <~fnz ;mask bits not altered
0015C7 1 CD 20 02 cmp fLDx+3 ;test flags
0015CA 1 D0 FE trap_ne
0015CC 1
0015CC 1 A0 00 ldy #0
0015CE 1 A5 0C lda zpt
0015D0 1 49 C3 eor #$c3
0015D2 1 C5 15 cmp zp1
0015D4 1 D0 FE trap_ne ;store to zp data
0015D6 1 84 0C sty zpt ;clear
0015D8 1 AD 03 02 lda abst
0015DB 1 49 C3 eor #$c3
0015DD 1 CD 18 02 cmp abs1
0015E0 1 D0 FE trap_ne ;store to abs data
0015E2 1 8C 03 02 sty abst ;clear
0015E5 1 A5 0D lda zpt+1
0015E7 1 49 C3 eor #$c3
0015E9 1 C5 16 cmp zp1+1
0015EB 1 D0 FE trap_ne ;store to zp+1 data
0015ED 1 84 0D sty zpt+1 ;clear
0015EF 1 AD 04 02 lda abst+1
0015F2 1 49 C3 eor #$c3
0015F4 1 CD 19 02 cmp abs1+1
0015F7 1 D0 FE trap_ne ;store to abs+1 data
0015F9 1 8C 04 02 sty abst+1 ;clear
0015FC 1 A5 0E lda zpt+2
0015FE 1 49 C3 eor #$c3
001600 1 C5 17 cmp zp1+2
001602 1 D0 FE trap_ne ;store to zp+2 data
001604 1 84 0E sty zpt+2 ;clear
001606 1 AD 05 02 lda abst+2
001609 1 49 C3 eor #$c3
00160B 1 CD 1A 02 cmp abs1+2
00160E 1 D0 FE trap_ne ;store to abs+2 data
001610 1 8C 05 02 sty abst+2 ;clear
001613 1 A5 0F lda zpt+3
001615 1 49 C3 eor #$c3
001617 1 C5 18 cmp zp1+3
001619 1 D0 FE trap_ne ;store to zp+3 data
00161B 1 84 0F sty zpt+3 ;clear
00161D 1 AD 06 02 lda abst+3
001620 1 49 C3 eor #$c3
001622 1 CD 1B 02 cmp abs1+3
001625 1 D0 FE trap_ne ;store to abs+3 data
001627 1 8C 06 02 sty abst+3 ;clear
00162A 1 AD 00 02 C9 next_test
00162E 1 14 D0 FE A9
001632 1 15 8D 00 02
001636 1
001636 1 ; testing load / store accumulator LDA / STA all addressing modes
001636 1 ; LDA / STA - zp,x / abs,x
001636 1 A2 03 ldx #3
001638 1 tldax:
001638 1 A9 00 48 28 set_stat 0
00163C 1 B5 15 lda zp1,x
00163E 1 08 php ;test stores do not alter flags
00163F 1 49 C3 eor #$c3
001641 1 28 plp
001642 1 9D 03 02 sta abst,x
001645 1 08 php ;flags after load/store sequence
001646 1 49 C3 eor #$c3
001648 1 DD 18 02 cmp abs1,x ;test result
00164B 1 D0 FE trap_ne
00164D 1 68 pla ;load status
00164E 1 49 30 eor_flag 0
001650 1 DD 1D 02 cmp fLDx,x ;test flags
001653 1 D0 FE trap_ne
001655 1 CA dex
001656 1 10 E0 bpl tldax
001658 1
001658 1 A2 03 ldx #3
00165A 1 tldax1:
00165A 1 A9 FF 48 28 set_stat $ff
00165E 1 B5 15 lda zp1,x
001660 1 08 php ;test stores do not alter flags
001661 1 49 C3 eor #$c3
001663 1 28 plp
001664 1 9D 03 02 sta abst,x
001667 1 08 php ;flags after load/store sequence
001668 1 49 C3 eor #$c3
00166A 1 DD 18 02 cmp abs1,x ;test result
00166D 1 D0 FE trap_ne
00166F 1 68 pla ;load status
001670 1 49 7D eor_flag <~fnz ;mask bits not altered
001672 1 DD 1D 02 cmp fLDx,x ;test flags
001675 1 D0 FE trap_ne
001677 1 CA dex
001678 1 10 E0 bpl tldax1
00167A 1
00167A 1 A2 03 ldx #3
00167C 1 tldax2:
00167C 1 A9 00 48 28 set_stat 0
001680 1 BD 18 02 lda abs1,x
001683 1 08 php ;test stores do not alter flags
001684 1 49 C3 eor #$c3
001686 1 28 plp
001687 1 95 0C sta zpt,x
001689 1 08 php ;flags after load/store sequence
00168A 1 49 C3 eor #$c3
00168C 1 D5 15 cmp zp1,x ;test result
00168E 1 D0 FE trap_ne
001690 1 68 pla ;load status
001691 1 49 30 eor_flag 0
001693 1 DD 1D 02 cmp fLDx,x ;test flags
001696 1 D0 FE trap_ne
001698 1 CA dex
001699 1 10 E1 bpl tldax2
00169B 1
00169B 1 A2 03 ldx #3
00169D 1 tldax3:
00169D 1 A9 FF 48 28 set_stat $ff
0016A1 1 BD 18 02 lda abs1,x
0016A4 1 08 php ;test stores do not alter flags
0016A5 1 49 C3 eor #$c3
0016A7 1 28 plp
0016A8 1 95 0C sta zpt,x
0016AA 1 08 php ;flags after load/store sequence
0016AB 1 49 C3 eor #$c3
0016AD 1 D5 15 cmp zp1,x ;test result
0016AF 1 D0 FE trap_ne
0016B1 1 68 pla ;load status
0016B2 1 49 7D eor_flag <~fnz ;mask bits not altered
0016B4 1 DD 1D 02 cmp fLDx,x ;test flags
0016B7 1 D0 FE trap_ne
0016B9 1 CA dex
0016BA 1 10 E1 bpl tldax3
0016BC 1
0016BC 1 A2 03 ldx #3 ;testing store result
0016BE 1 A0 00 ldy #0
0016C0 1 B5 0C tstax: lda zpt,x
0016C2 1 49 C3 eor #$c3
0016C4 1 D5 15 cmp zp1,x
0016C6 1 D0 FE trap_ne ;store to zp,x data
0016C8 1 94 0C sty zpt,x ;clear
0016CA 1 BD 03 02 lda abst,x
0016CD 1 49 C3 eor #$c3
0016CF 1 DD 18 02 cmp abs1,x
0016D2 1 D0 FE trap_ne ;store to abs,x data
0016D4 1 8A txa
0016D5 1 9D 03 02 sta abst,x ;clear
0016D8 1 CA dex
0016D9 1 10 E5 bpl tstax
0016DB 1 AD 00 02 C9 next_test
0016DF 1 15 D0 FE A9
0016E3 1 16 8D 00 02
0016E7 1
0016E7 1 ; LDA / STA - (zp),y / abs,y / (zp,x)
0016E7 1 A0 03 ldy #3
0016E9 1 tlday:
0016E9 1 A9 00 48 28 set_stat 0
0016ED 1 B1 26 lda (ind1),y
0016EF 1 08 php ;test stores do not alter flags
0016F0 1 49 C3 eor #$c3
0016F2 1 28 plp
0016F3 1 99 03 02 sta abst,y
0016F6 1 08 php ;flags after load/store sequence
0016F7 1 49 C3 eor #$c3
0016F9 1 D9 18 02 cmp abs1,y ;test result
0016FC 1 D0 FE trap_ne
0016FE 1 68 pla ;load status
0016FF 1 49 30 eor_flag 0
001701 1 D9 1D 02 cmp fLDx,y ;test flags
001704 1 D0 FE trap_ne
001706 1 88 dey
001707 1 10 E0 bpl tlday
001709 1
001709 1 A0 03 ldy #3
00170B 1 tlday1:
00170B 1 A9 FF 48 28 set_stat $ff
00170F 1 B1 26 lda (ind1),y
001711 1 08 php ;test stores do not alter flags
001712 1 49 C3 eor #$c3
001714 1 28 plp
001715 1 99 03 02 sta abst,y
001718 1 08 php ;flags after load/store sequence
001719 1 49 C3 eor #$c3
00171B 1 D9 18 02 cmp abs1,y ;test result
00171E 1 D0 FE trap_ne
001720 1 68 pla ;load status
001721 1 49 7D eor_flag <~fnz ;mask bits not altered
001723 1 D9 1D 02 cmp fLDx,y ;test flags
001726 1 D0 FE trap_ne
001728 1 88 dey
001729 1 10 E0 bpl tlday1
00172B 1
00172B 1 A0 03 ldy #3 ;testing store result
00172D 1 A2 00 ldx #0
00172F 1 B9 03 02 tstay: lda abst,y
001732 1 49 C3 eor #$c3
001734 1 D9 18 02 cmp abs1,y
001737 1 D0 FE trap_ne ;store to abs data
001739 1 8A txa
00173A 1 99 03 02 sta abst,y ;clear
00173D 1 88 dey
00173E 1 10 EF bpl tstay
001740 1
001740 1 A0 03 ldy #3
001742 1 tlday2:
001742 1 A9 00 48 28 set_stat 0
001746 1 B9 18 02 lda abs1,y
001749 1 08 php ;test stores do not alter flags
00174A 1 49 C3 eor #$c3
00174C 1 28 plp
00174D 1 91 32 sta (indt),y
00174F 1 08 php ;flags after load/store sequence
001750 1 49 C3 eor #$c3
001752 1 D1 26 cmp (ind1),y ;test result
001754 1 D0 FE trap_ne
001756 1 68 pla ;load status
001757 1 49 30 eor_flag 0
001759 1 D9 1D 02 cmp fLDx,y ;test flags
00175C 1 D0 FE trap_ne
00175E 1 88 dey
00175F 1 10 E1 bpl tlday2
001761 1
001761 1 A0 03 ldy #3
001763 1 tlday3:
001763 1 A9 FF 48 28 set_stat $ff
001767 1 B9 18 02 lda abs1,y
00176A 1 08 php ;test stores do not alter flags
00176B 1 49 C3 eor #$c3
00176D 1 28 plp
00176E 1 91 32 sta (indt),y
001770 1 08 php ;flags after load/store sequence
001771 1 49 C3 eor #$c3
001773 1 D1 26 cmp (ind1),y ;test result
001775 1 D0 FE trap_ne
001777 1 68 pla ;load status
001778 1 49 7D eor_flag <~fnz ;mask bits not altered
00177A 1 D9 1D 02 cmp fLDx,y ;test flags
00177D 1 D0 FE trap_ne
00177F 1 88 dey
001780 1 10 E1 bpl tlday3
001782 1
001782 1 A0 03 ldy #3 ;testing store result
001784 1 A2 00 ldx #0
001786 1 B9 03 02 tstay1: lda abst,y
001789 1 49 C3 eor #$c3
00178B 1 D9 18 02 cmp abs1,y
00178E 1 D0 FE trap_ne ;store to abs data
001790 1 8A txa
001791 1 99 03 02 sta abst,y ;clear
001794 1 88 dey
001795 1 10 EF bpl tstay1
001797 1
001797 1 A2 06 ldx #6
001799 1 A0 03 ldy #3
00179B 1 tldax4:
00179B 1 A9 00 48 28 set_stat 0
00179F 1 A1 26 lda (ind1,x)
0017A1 1 08 php ;test stores do not alter flags
0017A2 1 49 C3 eor #$c3
0017A4 1 28 plp
0017A5 1 81 32 sta (indt,x)
0017A7 1 08 php ;flags after load/store sequence
0017A8 1 49 C3 eor #$c3
0017AA 1 D9 18 02 cmp abs1,y ;test result
0017AD 1 D0 FE trap_ne
0017AF 1 68 pla ;load status
0017B0 1 49 30 eor_flag 0
0017B2 1 D9 1D 02 cmp fLDx,y ;test flags
0017B5 1 D0 FE trap_ne
0017B7 1 CA dex
0017B8 1 CA dex
0017B9 1 88 dey
0017BA 1 10 DF bpl tldax4
0017BC 1
0017BC 1 A2 06 ldx #6
0017BE 1 A0 03 ldy #3
0017C0 1 tldax5:
0017C0 1 A9 FF 48 28 set_stat $ff
0017C4 1 A1 26 lda (ind1,x)
0017C6 1 08 php ;test stores do not alter flags
0017C7 1 49 C3 eor #$c3
0017C9 1 28 plp
0017CA 1 81 32 sta (indt,x)
0017CC 1 08 php ;flags after load/store sequence
0017CD 1 49 C3 eor #$c3
0017CF 1 D9 18 02 cmp abs1,y ;test result
0017D2 1 D0 FE trap_ne
0017D4 1 68 pla ;load status
0017D5 1 49 7D eor_flag <~fnz ;mask bits not altered
0017D7 1 D9 1D 02 cmp fLDx,y ;test flags
0017DA 1 D0 FE trap_ne
0017DC 1 CA dex
0017DD 1 CA dex
0017DE 1 88 dey
0017DF 1 10 DF bpl tldax5
0017E1 1
0017E1 1 A0 03 ldy #3 ;testing store result
0017E3 1 A2 00 ldx #0
0017E5 1 B9 03 02 tstay2: lda abst,y
0017E8 1 49 C3 eor #$c3
0017EA 1 D9 18 02 cmp abs1,y
0017ED 1 D0 FE trap_ne ;store to abs data
0017EF 1 8A txa
0017F0 1 99 03 02 sta abst,y ;clear
0017F3 1 88 dey
0017F4 1 10 EF bpl tstay2
0017F6 1 AD 00 02 C9 next_test
0017FA 1 16 D0 FE A9
0017FE 1 17 8D 00 02
001802 1
001802 1 ; indexed wraparound test (only zp should wrap)
001802 1 A2 FD ldx #3+$fa
001804 1 B5 1B tldax6: lda <(zp1-$fa),x ;wrap on indexed zp
001806 1 9D 09 01 sta abst-$fa,x ;no STX abs,x!
001809 1 CA dex
00180A 1 E0 FA cpx #$fa
00180C 1 B0 F6 bcs tldax6
00180E 1 A2 FD ldx #3+$fa
001810 1 BD 1E 01 tldax7: lda abs1-$fa,x ;no wrap on indexed abs
001813 1 95 12 sta <(zpt-$fa),x
001815 1 CA dex
001816 1 E0 FA cpx #$fa
001818 1 B0 F6 bcs tldax7
00181A 1
00181A 1 A2 03 ldx #3 ;testing wraparound result
00181C 1 A0 00 ldy #0
00181E 1 B5 0C tstax1: lda zpt,x
001820 1 D5 15 cmp zp1,x
001822 1 D0 FE trap_ne ;store to zp,x data
001824 1 94 0C sty zpt,x ;clear
001826 1 BD 03 02 lda abst,x
001829 1 DD 18 02 cmp abs1,x
00182C 1 D0 FE trap_ne ;store to abs,x data
00182E 1 8A txa
00182F 1 9D 03 02 sta abst,x ;clear
001832 1 CA dex
001833 1 10 E9 bpl tstax1
001835 1
001835 1 A0 FB ldy #3+$f8
001837 1 A2 FE ldx #6+$f8
001839 1 A1 2E tlday4: lda (<(ind1-$f8),x) ;wrap on indexed zp indirect
00183B 1 99 0B 01 sta abst-$f8,y
00183E 1 CA dex
00183F 1 CA dex
001840 1 88 dey
001841 1 C0 F8 cpy #$f8
001843 1 B0 F4 bcs tlday4
001845 1 A0 03 ldy #3 ;testing wraparound result
001847 1 A2 00 ldx #0
001849 1 B9 03 02 tstay4: lda abst,y
00184C 1 D9 18 02 cmp abs1,y
00184F 1 D0 FE trap_ne ;store to abs data
001851 1 8A txa
001852 1 99 03 02 sta abst,y ;clear
001855 1 88 dey
001856 1 10 F1 bpl tstay4
001858 1
001858 1 A0 FB ldy #3+$f8
00185A 1 B9 20 01 tlday5: lda abs1-$f8,y ;no wrap on indexed abs
00185D 1 91 3A sta (inwt),y
00185F 1 88 dey
001860 1 C0 F8 cpy #$f8
001862 1 B0 F6 bcs tlday5
001864 1 A0 03 ldy #3 ;testing wraparound result
001866 1 A2 00 ldx #0
001868 1 B9 03 02 tstay5: lda abst,y
00186B 1 D9 18 02 cmp abs1,y
00186E 1 D0 FE trap_ne ;store to abs data
001870 1 8A txa
001871 1 99 03 02 sta abst,y ;clear
001874 1 88 dey
001875 1 10 F1 bpl tstay5
001877 1
001877 1 A0 FB ldy #3+$f8
001879 1 A2 FE ldx #6+$f8
00187B 1 B1 30 tlday6: lda (inw1),y ;no wrap on zp indirect indexed
00187D 1 81 3A sta (<(indt-$f8),x)
00187F 1 CA dex
001880 1 CA dex
001881 1 88 dey
001882 1 C0 F8 cpy #$f8
001884 1 B0 F5 bcs tlday6
001886 1 A0 03 ldy #3 ;testing wraparound result
001888 1 A2 00 ldx #0
00188A 1 B9 03 02 tstay6: lda abst,y
00188D 1 D9 18 02 cmp abs1,y
001890 1 D0 FE trap_ne ;store to abs data
001892 1 8A txa
001893 1 99 03 02 sta abst,y ;clear
001896 1 88 dey
001897 1 10 F1 bpl tstay6
001899 1 AD 00 02 C9 next_test
00189D 1 17 D0 FE A9
0018A1 1 18 8D 00 02
0018A5 1
0018A5 1 ; LDA / STA - zp / abs / #
0018A5 1 A9 00 48 28 set_stat 0
0018A9 1 A5 15 lda zp1
0018AB 1 08 php ;test stores do not alter flags
0018AC 1 49 C3 eor #$c3
0018AE 1 28 plp
0018AF 1 8D 03 02 sta abst
0018B2 1 08 php ;flags after load/store sequence
0018B3 1 49 C3 eor #$c3
0018B5 1 C9 C3 cmp #$c3 ;test result
0018B7 1 D0 FE trap_ne
0018B9 1 68 pla ;load status
0018BA 1 49 30 eor_flag 0
0018BC 1 CD 1D 02 cmp fLDx ;test flags
0018BF 1 D0 FE trap_ne
0018C1 1 A9 00 48 28 set_stat 0
0018C5 1 A5 16 lda zp1+1
0018C7 1 08 php ;test stores do not alter flags
0018C8 1 49 C3 eor #$c3
0018CA 1 28 plp
0018CB 1 8D 04 02 sta abst+1
0018CE 1 08 php ;flags after load/store sequence
0018CF 1 49 C3 eor #$c3
0018D1 1 C9 82 cmp #$82 ;test result
0018D3 1 D0 FE trap_ne
0018D5 1 68 pla ;load status
0018D6 1 49 30 eor_flag 0
0018D8 1 CD 1E 02 cmp fLDx+1 ;test flags
0018DB 1 D0 FE trap_ne
0018DD 1 A9 00 48 28 set_stat 0
0018E1 1 A5 17 lda zp1+2
0018E3 1 08 php ;test stores do not alter flags
0018E4 1 49 C3 eor #$c3
0018E6 1 28 plp
0018E7 1 8D 05 02 sta abst+2
0018EA 1 08 php ;flags after load/store sequence
0018EB 1 49 C3 eor #$c3
0018ED 1 C9 41 cmp #$41 ;test result
0018EF 1 D0 FE trap_ne
0018F1 1 68 pla ;load status
0018F2 1 49 30 eor_flag 0
0018F4 1 CD 1F 02 cmp fLDx+2 ;test flags
0018F7 1 D0 FE trap_ne
0018F9 1 A9 00 48 28 set_stat 0
0018FD 1 A5 18 lda zp1+3
0018FF 1 08 php ;test stores do not alter flags
001900 1 49 C3 eor #$c3
001902 1 28 plp
001903 1 8D 06 02 sta abst+3
001906 1 08 php ;flags after load/store sequence
001907 1 49 C3 eor #$c3
001909 1 C9 00 cmp #0 ;test result
00190B 1 D0 FE trap_ne
00190D 1 68 pla ;load status
00190E 1 49 30 eor_flag 0
001910 1 CD 20 02 cmp fLDx+3 ;test flags
001913 1 D0 FE trap_ne
001915 1 A9 FF 48 28 set_stat $ff
001919 1 A5 15 lda zp1
00191B 1 08 php ;test stores do not alter flags
00191C 1 49 C3 eor #$c3
00191E 1 28 plp
00191F 1 8D 03 02 sta abst
001922 1 08 php ;flags after load/store sequence
001923 1 49 C3 eor #$c3
001925 1 C9 C3 cmp #$c3 ;test result
001927 1 D0 FE trap_ne
001929 1 68 pla ;load status
00192A 1 49 7D eor_flag <~fnz ;mask bits not altered
00192C 1 CD 1D 02 cmp fLDx ;test flags
00192F 1 D0 FE trap_ne
001931 1 A9 FF 48 28 set_stat $ff
001935 1 A5 16 lda zp1+1
001937 1 08 php ;test stores do not alter flags
001938 1 49 C3 eor #$c3
00193A 1 28 plp
00193B 1 8D 04 02 sta abst+1
00193E 1 08 php ;flags after load/store sequence
00193F 1 49 C3 eor #$c3
001941 1 C9 82 cmp #$82 ;test result
001943 1 D0 FE trap_ne
001945 1 68 pla ;load status
001946 1 49 7D eor_flag <~fnz ;mask bits not altered
001948 1 CD 1E 02 cmp fLDx+1 ;test flags
00194B 1 D0 FE trap_ne
00194D 1 A9 FF 48 28 set_stat $ff
001951 1 A5 17 lda zp1+2
001953 1 08 php ;test stores do not alter flags
001954 1 49 C3 eor #$c3
001956 1 28 plp
001957 1 8D 05 02 sta abst+2
00195A 1 08 php ;flags after load/store sequence
00195B 1 49 C3 eor #$c3
00195D 1 C9 41 cmp #$41 ;test result
00195F 1 D0 FE trap_ne
001961 1 68 pla ;load status
001962 1 49 7D eor_flag <~fnz ;mask bits not altered
001964 1 CD 1F 02 cmp fLDx+2 ;test flags
001967 1 D0 FE trap_ne
001969 1 A9 FF 48 28 set_stat $ff
00196D 1 A5 18 lda zp1+3
00196F 1 08 php ;test stores do not alter flags
001970 1 49 C3 eor #$c3
001972 1 28 plp
001973 1 8D 06 02 sta abst+3
001976 1 08 php ;flags after load/store sequence
001977 1 49 C3 eor #$c3
001979 1 C9 00 cmp #0 ;test result
00197B 1 D0 FE trap_ne
00197D 1 68 pla ;load status
00197E 1 49 7D eor_flag <~fnz ;mask bits not altered
001980 1 CD 20 02 cmp fLDx+3 ;test flags
001983 1 D0 FE trap_ne
001985 1 A9 00 48 28 set_stat 0
001989 1 AD 18 02 lda abs1
00198C 1 08 php ;test stores do not alter flags
00198D 1 49 C3 eor #$c3
00198F 1 28 plp
001990 1 85 0C sta zpt
001992 1 08 php ;flags after load/store sequence
001993 1 49 C3 eor #$c3
001995 1 C5 15 cmp zp1 ;test result
001997 1 D0 FE trap_ne
001999 1 68 pla ;load status
00199A 1 49 30 eor_flag 0
00199C 1 CD 1D 02 cmp fLDx ;test flags
00199F 1 D0 FE trap_ne
0019A1 1 A9 00 48 28 set_stat 0
0019A5 1 AD 19 02 lda abs1+1
0019A8 1 08 php ;test stores do not alter flags
0019A9 1 49 C3 eor #$c3
0019AB 1 28 plp
0019AC 1 85 0D sta zpt+1
0019AE 1 08 php ;flags after load/store sequence
0019AF 1 49 C3 eor #$c3
0019B1 1 C5 16 cmp zp1+1 ;test result
0019B3 1 D0 FE trap_ne
0019B5 1 68 pla ;load status
0019B6 1 49 30 eor_flag 0
0019B8 1 CD 1E 02 cmp fLDx+1 ;test flags
0019BB 1 D0 FE trap_ne
0019BD 1 A9 00 48 28 set_stat 0
0019C1 1 AD 1A 02 lda abs1+2
0019C4 1 08 php ;test stores do not alter flags
0019C5 1 49 C3 eor #$c3
0019C7 1 28 plp
0019C8 1 85 0E sta zpt+2
0019CA 1 08 php ;flags after load/store sequence
0019CB 1 49 C3 eor #$c3
0019CD 1 C5 17 cmp zp1+2 ;test result
0019CF 1 D0 FE trap_ne
0019D1 1 68 pla ;load status
0019D2 1 49 30 eor_flag 0
0019D4 1 CD 1F 02 cmp fLDx+2 ;test flags
0019D7 1 D0 FE trap_ne
0019D9 1 A9 00 48 28 set_stat 0
0019DD 1 AD 1B 02 lda abs1+3
0019E0 1 08 php ;test stores do not alter flags
0019E1 1 49 C3 eor #$c3
0019E3 1 28 plp
0019E4 1 85 0F sta zpt+3
0019E6 1 08 php ;flags after load/store sequence
0019E7 1 49 C3 eor #$c3
0019E9 1 C5 18 cmp zp1+3 ;test result
0019EB 1 D0 FE trap_ne
0019ED 1 68 pla ;load status
0019EE 1 49 30 eor_flag 0
0019F0 1 CD 20 02 cmp fLDx+3 ;test flags
0019F3 1 D0 FE trap_ne
0019F5 1 A9 FF 48 28 set_stat $ff
0019F9 1 AD 18 02 lda abs1
0019FC 1 08 php ;test stores do not alter flags
0019FD 1 49 C3 eor #$c3
0019FF 1 28 plp
001A00 1 85 0C sta zpt
001A02 1 08 php ;flags after load/store sequence
001A03 1 49 C3 eor #$c3
001A05 1 C5 15 cmp zp1 ;test result
001A07 1 D0 FE trap_ne
001A09 1 68 pla ;load status
001A0A 1 49 7D eor_flag <~fnz ;mask bits not altered
001A0C 1 CD 1D 02 cmp fLDx ;test flags
001A0F 1 D0 FE trap_ne
001A11 1 A9 FF 48 28 set_stat $ff
001A15 1 AD 19 02 lda abs1+1
001A18 1 08 php ;test stores do not alter flags
001A19 1 49 C3 eor #$c3
001A1B 1 28 plp
001A1C 1 85 0D sta zpt+1
001A1E 1 08 php ;flags after load/store sequence
001A1F 1 49 C3 eor #$c3
001A21 1 C5 16 cmp zp1+1 ;test result
001A23 1 D0 FE trap_ne
001A25 1 68 pla ;load status
001A26 1 49 7D eor_flag <~fnz ;mask bits not altered
001A28 1 CD 1E 02 cmp fLDx+1 ;test flags
001A2B 1 D0 FE trap_ne
001A2D 1 A9 FF 48 28 set_stat $ff
001A31 1 AD 1A 02 lda abs1+2
001A34 1 08 php ;test stores do not alter flags
001A35 1 49 C3 eor #$c3
001A37 1 28 plp
001A38 1 85 0E sta zpt+2
001A3A 1 08 php ;flags after load/store sequence
001A3B 1 49 C3 eor #$c3
001A3D 1 C5 17 cmp zp1+2 ;test result
001A3F 1 D0 FE trap_ne
001A41 1 68 pla ;load status
001A42 1 49 7D eor_flag <~fnz ;mask bits not altered
001A44 1 CD 1F 02 cmp fLDx+2 ;test flags
001A47 1 D0 FE trap_ne
001A49 1 A9 FF 48 28 set_stat $ff
001A4D 1 AD 1B 02 lda abs1+3
001A50 1 08 php ;test stores do not alter flags
001A51 1 49 C3 eor #$c3
001A53 1 28 plp
001A54 1 85 0F sta zpt+3
001A56 1 08 php ;flags after load/store sequence
001A57 1 49 C3 eor #$c3
001A59 1 C5 18 cmp zp1+3 ;test result
001A5B 1 D0 FE trap_ne
001A5D 1 68 pla ;load status
001A5E 1 49 7D eor_flag <~fnz ;mask bits not altered
001A60 1 CD 20 02 cmp fLDx+3 ;test flags
001A63 1 D0 FE trap_ne
001A65 1 A9 00 48 28 set_stat 0
001A69 1 A9 C3 lda #$c3
001A6B 1 08 php
001A6C 1 CD 18 02 cmp abs1 ;test result
001A6F 1 D0 FE trap_ne
001A71 1 68 pla ;load status
001A72 1 49 30 eor_flag 0
001A74 1 CD 1D 02 cmp fLDx ;test flags
001A77 1 D0 FE trap_ne
001A79 1 A9 00 48 28 set_stat 0
001A7D 1 A9 82 lda #$82
001A7F 1 08 php
001A80 1 CD 19 02 cmp abs1+1 ;test result
001A83 1 D0 FE trap_ne
001A85 1 68 pla ;load status
001A86 1 49 30 eor_flag 0
001A88 1 CD 1E 02 cmp fLDx+1 ;test flags
001A8B 1 D0 FE trap_ne
001A8D 1 A9 00 48 28 set_stat 0
001A91 1 A9 41 lda #$41
001A93 1 08 php
001A94 1 CD 1A 02 cmp abs1+2 ;test result
001A97 1 D0 FE trap_ne
001A99 1 68 pla ;load status
001A9A 1 49 30 eor_flag 0
001A9C 1 CD 1F 02 cmp fLDx+2 ;test flags
001A9F 1 D0 FE trap_ne
001AA1 1 A9 00 48 28 set_stat 0
001AA5 1 A9 00 lda #0
001AA7 1 08 php
001AA8 1 CD 1B 02 cmp abs1+3 ;test result
001AAB 1 D0 FE trap_ne
001AAD 1 68 pla ;load status
001AAE 1 49 30 eor_flag 0
001AB0 1 CD 20 02 cmp fLDx+3 ;test flags
001AB3 1 D0 FE trap_ne
001AB5 1
001AB5 1 A9 FF 48 28 set_stat $ff
001AB9 1 A9 C3 lda #$c3
001ABB 1 08 php
001ABC 1 CD 18 02 cmp abs1 ;test result
001ABF 1 D0 FE trap_ne
001AC1 1 68 pla ;load status
001AC2 1 49 7D eor_flag <~fnz ;mask bits not altered
001AC4 1 CD 1D 02 cmp fLDx ;test flags
001AC7 1 D0 FE trap_ne
001AC9 1 A9 FF 48 28 set_stat $ff
001ACD 1 A9 82 lda #$82
001ACF 1 08 php
001AD0 1 CD 19 02 cmp abs1+1 ;test result
001AD3 1 D0 FE trap_ne
001AD5 1 68 pla ;load status
001AD6 1 49 7D eor_flag <~fnz ;mask bits not altered
001AD8 1 CD 1E 02 cmp fLDx+1 ;test flags
001ADB 1 D0 FE trap_ne
001ADD 1 A9 FF 48 28 set_stat $ff
001AE1 1 A9 41 lda #$41
001AE3 1 08 php
001AE4 1 CD 1A 02 cmp abs1+2 ;test result
001AE7 1 D0 FE trap_ne
001AE9 1 68 pla ;load status
001AEA 1 49 7D eor_flag <~fnz ;mask bits not altered
001AEC 1 CD 1F 02 cmp fLDx+2 ;test flags
001AEF 1 D0 FE trap_ne
001AF1 1 A9 FF 48 28 set_stat $ff
001AF5 1 A9 00 lda #0
001AF7 1 08 php
001AF8 1 CD 1B 02 cmp abs1+3 ;test result
001AFB 1 D0 FE trap_ne
001AFD 1 68 pla ;load status
001AFE 1 49 7D eor_flag <~fnz ;mask bits not altered
001B00 1 CD 20 02 cmp fLDx+3 ;test flags
001B03 1 D0 FE trap_ne
001B05 1
001B05 1 A2 00 ldx #0
001B07 1 A5 0C lda zpt
001B09 1 49 C3 eor #$c3
001B0B 1 C5 15 cmp zp1
001B0D 1 D0 FE trap_ne ;store to zp data
001B0F 1 86 0C stx zpt ;clear
001B11 1 AD 03 02 lda abst
001B14 1 49 C3 eor #$c3
001B16 1 CD 18 02 cmp abs1
001B19 1 D0 FE trap_ne ;store to abs data
001B1B 1 8E 03 02 stx abst ;clear
001B1E 1 A5 0D lda zpt+1
001B20 1 49 C3 eor #$c3
001B22 1 C5 16 cmp zp1+1
001B24 1 D0 FE trap_ne ;store to zp data
001B26 1 86 0D stx zpt+1 ;clear
001B28 1 AD 04 02 lda abst+1
001B2B 1 49 C3 eor #$c3
001B2D 1 CD 19 02 cmp abs1+1
001B30 1 D0 FE trap_ne ;store to abs data
001B32 1 8E 04 02 stx abst+1 ;clear
001B35 1 A5 0E lda zpt+2
001B37 1 49 C3 eor #$c3
001B39 1 C5 17 cmp zp1+2
001B3B 1 D0 FE trap_ne ;store to zp data
001B3D 1 86 0E stx zpt+2 ;clear
001B3F 1 AD 05 02 lda abst+2
001B42 1 49 C3 eor #$c3
001B44 1 CD 1A 02 cmp abs1+2
001B47 1 D0 FE trap_ne ;store to abs data
001B49 1 8E 05 02 stx abst+2 ;clear
001B4C 1 A5 0F lda zpt+3
001B4E 1 49 C3 eor #$c3
001B50 1 C5 18 cmp zp1+3
001B52 1 D0 FE trap_ne ;store to zp data
001B54 1 86 0F stx zpt+3 ;clear
001B56 1 AD 06 02 lda abst+3
001B59 1 49 C3 eor #$c3
001B5B 1 CD 1B 02 cmp abs1+3
001B5E 1 D0 FE trap_ne ;store to abs data
001B60 1 8E 06 02 stx abst+3 ;clear
001B63 1 AD 00 02 C9 next_test
001B67 1 18 D0 FE A9
001B6B 1 19 8D 00 02
001B6F 1
001B6F 1 ; testing bit test & compares BIT CPX CPY CMP all addressing modes
001B6F 1 ; BIT - zp / abs
001B6F 1 A9 00 48 A9 set_a $ff,0
001B73 1 FF 28
001B75 1 24 18 bit zp1+3 ;00 - should set Z / clear NV
001B77 1 08 C9 FF D0 tst_a $ff,fz
001B7B 1 FE 68 48 C9
001B7F 1 32 D0 FE 28
001B83 1 A9 00 48 A9 set_a 1,0
001B87 1 01 28
001B89 1 24 17 bit zp1+2 ;41 - should set V (M6) / clear NZ
001B8B 1 08 C9 01 D0 tst_a 1,fv
001B8F 1 FE 68 48 C9
001B93 1 70 D0 FE 28
001B97 1 A9 00 48 A9 set_a 1,0
001B9B 1 01 28
001B9D 1 24 16 bit zp1+1 ;82 - should set N (M7) & Z / clear V
001B9F 1 08 C9 01 D0 tst_a 1,fnz
001BA3 1 FE 68 48 C9
001BA7 1 B2 D0 FE 28
001BAB 1 A9 00 48 A9 set_a 1,0
001BAF 1 01 28
001BB1 1 24 15 bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z
001BB3 1 08 C9 01 D0 tst_a 1,fnv
001BB7 1 FE 68 48 C9
001BBB 1 F0 D0 FE 28
001BBF 1
001BBF 1 A9 FF 48 A9 set_a $ff,$ff
001BC3 1 FF 28
001BC5 1 24 18 bit zp1+3 ;00 - should set Z / clear NV
001BC7 1 08 C9 FF D0 tst_a $ff,~fnv
001BCB 1 FE 68 48 C9
001BCF 1 3F D0 FE 28
001BD3 1 A9 FF 48 A9 set_a 1,$ff
001BD7 1 01 28
001BD9 1 24 17 bit zp1+2 ;41 - should set V (M6) / clear NZ
001BDB 1 08 C9 01 D0 tst_a 1,~fnz
001BDF 1 FE 68 48 C9
001BE3 1 7D D0 FE 28
001BE7 1 A9 FF 48 A9 set_a 1,$ff
001BEB 1 01 28
001BED 1 24 16 bit zp1+1 ;82 - should set N (M7) & Z / clear V
001BEF 1 08 C9 01 D0 tst_a 1,~fv
001BF3 1 FE 68 48 C9
001BF7 1 BF D0 FE 28
001BFB 1 A9 FF 48 A9 set_a 1,$ff
001BFF 1 01 28
001C01 1 24 15 bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z
001C03 1 08 C9 01 D0 tst_a 1,~fz
001C07 1 FE 68 48 C9
001C0B 1 FD D0 FE 28
001C0F 1
001C0F 1 A9 00 48 A9 set_a $ff,0
001C13 1 FF 28
001C15 1 2C 1B 02 bit abs1+3 ;00 - should set Z / clear NV
001C18 1 08 C9 FF D0 tst_a $ff,fz
001C1C 1 FE 68 48 C9
001C20 1 32 D0 FE 28
001C24 1 A9 00 48 A9 set_a 1,0
001C28 1 01 28
001C2A 1 2C 1A 02 bit abs1+2 ;41 - should set V (M6) / clear NZ
001C2D 1 08 C9 01 D0 tst_a 1,fv
001C31 1 FE 68 48 C9
001C35 1 70 D0 FE 28
001C39 1 A9 00 48 A9 set_a 1,0
001C3D 1 01 28
001C3F 1 2C 19 02 bit abs1+1 ;82 - should set N (M7) & Z / clear V
001C42 1 08 C9 01 D0 tst_a 1,fnz
001C46 1 FE 68 48 C9
001C4A 1 B2 D0 FE 28
001C4E 1 A9 00 48 A9 set_a 1,0
001C52 1 01 28
001C54 1 2C 18 02 bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z
001C57 1 08 C9 01 D0 tst_a 1,fnv
001C5B 1 FE 68 48 C9
001C5F 1 F0 D0 FE 28
001C63 1
001C63 1 A9 FF 48 A9 set_a $ff,$ff
001C67 1 FF 28
001C69 1 2C 1B 02 bit abs1+3 ;00 - should set Z / clear NV
001C6C 1 08 C9 FF D0 tst_a $ff,~fnv
001C70 1 FE 68 48 C9
001C74 1 3F D0 FE 28
001C78 1 A9 FF 48 A9 set_a 1,$ff
001C7C 1 01 28
001C7E 1 2C 1A 02 bit abs1+2 ;41 - should set V (M6) / clear NZ
001C81 1 08 C9 01 D0 tst_a 1,~fnz
001C85 1 FE 68 48 C9
001C89 1 7D D0 FE 28
001C8D 1 A9 FF 48 A9 set_a 1,$ff
001C91 1 01 28
001C93 1 2C 19 02 bit abs1+1 ;82 - should set N (M7) & Z / clear V
001C96 1 08 C9 01 D0 tst_a 1,~fv
001C9A 1 FE 68 48 C9
001C9E 1 BF D0 FE 28
001CA2 1 A9 FF 48 A9 set_a 1,$ff
001CA6 1 01 28
001CA8 1 2C 18 02 bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z
001CAB 1 08 C9 01 D0 tst_a 1,~fz
001CAF 1 FE 68 48 C9
001CB3 1 FD D0 FE 28
001CB7 1 AD 00 02 C9 next_test
001CBB 1 19 D0 FE A9
001CBF 1 1A 8D 00 02
001CC3 1
001CC3 1 ; CPX - zp / abs / #
001CC3 1 A9 00 48 A2 set_x $80,0
001CC7 1 80 28
001CC9 1 E4 19 cpx zp7f
001CCB 1 08 68 48 C9 tst_stat fc
001CCF 1 31 D0 FE 28
001CD3 1 CA dex
001CD4 1 E4 19 cpx zp7f
001CD6 1 08 68 48 C9 tst_stat fzc
001CDA 1 33 D0 FE 28
001CDE 1 CA dex
001CDF 1 E4 19 cpx zp7f
001CE1 1 08 E0 7E D0 tst_x $7e,fn
001CE5 1 FE 68 48 C9
001CE9 1 B0 D0 FE 28
001CED 1 A9 FF 48 A2 set_x $80,$ff
001CF1 1 80 28
001CF3 1 E4 19 cpx zp7f
001CF5 1 08 68 48 C9 tst_stat ~fnz
001CF9 1 7D D0 FE 28
001CFD 1 CA dex
001CFE 1 E4 19 cpx zp7f
001D00 1 08 68 48 C9 tst_stat ~fn
001D04 1 7F D0 FE 28
001D08 1 CA dex
001D09 1 E4 19 cpx zp7f
001D0B 1 08 E0 7E D0 tst_x $7e,~fzc
001D0F 1 FE 68 48 C9
001D13 1 FC D0 FE 28
001D17 1
001D17 1 A9 00 48 A2 set_x $80,0
001D1B 1 80 28
001D1D 1 EC 1C 02 cpx abs7f
001D20 1 08 68 48 C9 tst_stat fc
001D24 1 31 D0 FE 28
001D28 1 CA dex
001D29 1 EC 1C 02 cpx abs7f
001D2C 1 08 68 48 C9 tst_stat fzc
001D30 1 33 D0 FE 28
001D34 1 CA dex
001D35 1 EC 1C 02 cpx abs7f
001D38 1 08 E0 7E D0 tst_x $7e,fn
001D3C 1 FE 68 48 C9
001D40 1 B0 D0 FE 28
001D44 1 A9 FF 48 A2 set_x $80,$ff
001D48 1 80 28
001D4A 1 EC 1C 02 cpx abs7f
001D4D 1 08 68 48 C9 tst_stat ~fnz
001D51 1 7D D0 FE 28
001D55 1 CA dex
001D56 1 EC 1C 02 cpx abs7f
001D59 1 08 68 48 C9 tst_stat ~fn
001D5D 1 7F D0 FE 28
001D61 1 CA dex
001D62 1 EC 1C 02 cpx abs7f
001D65 1 08 E0 7E D0 tst_x $7e,~fzc
001D69 1 FE 68 48 C9
001D6D 1 FC D0 FE 28
001D71 1
001D71 1 A9 00 48 A2 set_x $80,0
001D75 1 80 28
001D77 1 E0 7F cpx #$7f
001D79 1 08 68 48 C9 tst_stat fc
001D7D 1 31 D0 FE 28
001D81 1 CA dex
001D82 1 E0 7F cpx #$7f
001D84 1 08 68 48 C9 tst_stat fzc
001D88 1 33 D0 FE 28
001D8C 1 CA dex
001D8D 1 E0 7F cpx #$7f
001D8F 1 08 E0 7E D0 tst_x $7e,fn
001D93 1 FE 68 48 C9
001D97 1 B0 D0 FE 28
001D9B 1 A9 FF 48 A2 set_x $80,$ff
001D9F 1 80 28
001DA1 1 E0 7F cpx #$7f
001DA3 1 08 68 48 C9 tst_stat ~fnz
001DA7 1 7D D0 FE 28
001DAB 1 CA dex
001DAC 1 E0 7F cpx #$7f
001DAE 1 08 68 48 C9 tst_stat ~fn
001DB2 1 7F D0 FE 28
001DB6 1 CA dex
001DB7 1 E0 7F cpx #$7f
001DB9 1 08 E0 7E D0 tst_x $7e,~fzc
001DBD 1 FE 68 48 C9
001DC1 1 FC D0 FE 28
001DC5 1 AD 00 02 C9 next_test
001DC9 1 1A D0 FE A9
001DCD 1 1B 8D 00 02
001DD1 1
001DD1 1 ; CPY - zp / abs / #
001DD1 1 A9 00 48 A0 set_y $80,0
001DD5 1 80 28
001DD7 1 C4 19 cpy zp7f
001DD9 1 08 68 48 C9 tst_stat fc
001DDD 1 31 D0 FE 28
001DE1 1 88 dey
001DE2 1 C4 19 cpy zp7f
001DE4 1 08 68 48 C9 tst_stat fzc
001DE8 1 33 D0 FE 28
001DEC 1 88 dey
001DED 1 C4 19 cpy zp7f
001DEF 1 08 C0 7E D0 tst_y $7e,fn
001DF3 1 FE 68 48 C9
001DF7 1 B0 D0 FE 28
001DFB 1 A9 FF 48 A0 set_y $80,$ff
001DFF 1 80 28
001E01 1 C4 19 cpy zp7f
001E03 1 08 68 48 C9 tst_stat ~fnz
001E07 1 7D D0 FE 28
001E0B 1 88 dey
001E0C 1 C4 19 cpy zp7f
001E0E 1 08 68 48 C9 tst_stat ~fn
001E12 1 7F D0 FE 28
001E16 1 88 dey
001E17 1 C4 19 cpy zp7f
001E19 1 08 C0 7E D0 tst_y $7e,~fzc
001E1D 1 FE 68 48 C9
001E21 1 FC D0 FE 28
001E25 1
001E25 1 A9 00 48 A0 set_y $80,0
001E29 1 80 28
001E2B 1 CC 1C 02 cpy abs7f
001E2E 1 08 68 48 C9 tst_stat fc
001E32 1 31 D0 FE 28
001E36 1 88 dey
001E37 1 CC 1C 02 cpy abs7f
001E3A 1 08 68 48 C9 tst_stat fzc
001E3E 1 33 D0 FE 28
001E42 1 88 dey
001E43 1 CC 1C 02 cpy abs7f
001E46 1 08 C0 7E D0 tst_y $7e,fn
001E4A 1 FE 68 48 C9
001E4E 1 B0 D0 FE 28
001E52 1 A9 FF 48 A0 set_y $80,$ff
001E56 1 80 28
001E58 1 CC 1C 02 cpy abs7f
001E5B 1 08 68 48 C9 tst_stat ~fnz
001E5F 1 7D D0 FE 28
001E63 1 88 dey
001E64 1 CC 1C 02 cpy abs7f
001E67 1 08 68 48 C9 tst_stat ~fn
001E6B 1 7F D0 FE 28
001E6F 1 88 dey
001E70 1 CC 1C 02 cpy abs7f
001E73 1 08 C0 7E D0 tst_y $7e,~fzc
001E77 1 FE 68 48 C9
001E7B 1 FC D0 FE 28
001E7F 1
001E7F 1 A9 00 48 A0 set_y $80,0
001E83 1 80 28
001E85 1 C0 7F cpy #$7f
001E87 1 08 68 48 C9 tst_stat fc
001E8B 1 31 D0 FE 28
001E8F 1 88 dey
001E90 1 C0 7F cpy #$7f
001E92 1 08 68 48 C9 tst_stat fzc
001E96 1 33 D0 FE 28
001E9A 1 88 dey
001E9B 1 C0 7F cpy #$7f
001E9D 1 08 C0 7E D0 tst_y $7e,fn
001EA1 1 FE 68 48 C9
001EA5 1 B0 D0 FE 28
001EA9 1 A9 FF 48 A0 set_y $80,$ff
001EAD 1 80 28
001EAF 1 C0 7F cpy #$7f
001EB1 1 08 68 48 C9 tst_stat ~fnz
001EB5 1 7D D0 FE 28
001EB9 1 88 dey
001EBA 1 C0 7F cpy #$7f
001EBC 1 08 68 48 C9 tst_stat ~fn
001EC0 1 7F D0 FE 28
001EC4 1 88 dey
001EC5 1 C0 7F cpy #$7f
001EC7 1 08 C0 7E D0 tst_y $7e,~fzc
001ECB 1 FE 68 48 C9
001ECF 1 FC D0 FE 28
001ED3 1 AD 00 02 C9 next_test
001ED7 1 1B D0 FE A9
001EDB 1 1C 8D 00 02
001EDF 1
001EDF 1 ; CMP - zp / abs / #
001EDF 1 A9 00 48 A9 set_a $80,0
001EE3 1 80 28
001EE5 1 C5 19 cmp zp7f
001EE7 1 08 C9 80 D0 tst_a $80,fc
001EEB 1 FE 68 48 C9
001EEF 1 31 D0 FE 28
001EF3 1 A9 00 48 A9 set_a $7f,0
001EF7 1 7F 28
001EF9 1 C5 19 cmp zp7f
001EFB 1 08 C9 7F D0 tst_a $7f,fzc
001EFF 1 FE 68 48 C9
001F03 1 33 D0 FE 28
001F07 1 A9 00 48 A9 set_a $7e,0
001F0B 1 7E 28
001F0D 1 C5 19 cmp zp7f
001F0F 1 08 C9 7E D0 tst_a $7e,fn
001F13 1 FE 68 48 C9
001F17 1 B0 D0 FE 28
001F1B 1 A9 FF 48 A9 set_a $80,$ff
001F1F 1 80 28
001F21 1 C5 19 cmp zp7f
001F23 1 08 C9 80 D0 tst_a $80,~fnz
001F27 1 FE 68 48 C9
001F2B 1 7D D0 FE 28
001F2F 1 A9 FF 48 A9 set_a $7f,$ff
001F33 1 7F 28
001F35 1 C5 19 cmp zp7f
001F37 1 08 C9 7F D0 tst_a $7f,~fn
001F3B 1 FE 68 48 C9
001F3F 1 7F D0 FE 28
001F43 1 A9 FF 48 A9 set_a $7e,$ff
001F47 1 7E 28
001F49 1 C5 19 cmp zp7f
001F4B 1 08 C9 7E D0 tst_a $7e,~fzc
001F4F 1 FE 68 48 C9
001F53 1 FC D0 FE 28
001F57 1
001F57 1 A9 00 48 A9 set_a $80,0
001F5B 1 80 28
001F5D 1 CD 1C 02 cmp abs7f
001F60 1 08 C9 80 D0 tst_a $80,fc
001F64 1 FE 68 48 C9
001F68 1 31 D0 FE 28
001F6C 1 A9 00 48 A9 set_a $7f,0
001F70 1 7F 28
001F72 1 CD 1C 02 cmp abs7f
001F75 1 08 C9 7F D0 tst_a $7f,fzc
001F79 1 FE 68 48 C9
001F7D 1 33 D0 FE 28
001F81 1 A9 00 48 A9 set_a $7e,0
001F85 1 7E 28
001F87 1 CD 1C 02 cmp abs7f
001F8A 1 08 C9 7E D0 tst_a $7e,fn
001F8E 1 FE 68 48 C9
001F92 1 B0 D0 FE 28
001F96 1 A9 FF 48 A9 set_a $80,$ff
001F9A 1 80 28
001F9C 1 CD 1C 02 cmp abs7f
001F9F 1 08 C9 80 D0 tst_a $80,~fnz
001FA3 1 FE 68 48 C9
001FA7 1 7D D0 FE 28
001FAB 1 A9 FF 48 A9 set_a $7f,$ff
001FAF 1 7F 28
001FB1 1 CD 1C 02 cmp abs7f
001FB4 1 08 C9 7F D0 tst_a $7f,~fn
001FB8 1 FE 68 48 C9
001FBC 1 7F D0 FE 28
001FC0 1 A9 FF 48 A9 set_a $7e,$ff
001FC4 1 7E 28
001FC6 1 CD 1C 02 cmp abs7f
001FC9 1 08 C9 7E D0 tst_a $7e,~fzc
001FCD 1 FE 68 48 C9
001FD1 1 FC D0 FE 28
001FD5 1
001FD5 1 A9 00 48 A9 set_a $80,0
001FD9 1 80 28
001FDB 1 C9 7F cmp #$7f
001FDD 1 08 C9 80 D0 tst_a $80,fc
001FE1 1 FE 68 48 C9
001FE5 1 31 D0 FE 28
001FE9 1 A9 00 48 A9 set_a $7f,0
001FED 1 7F 28
001FEF 1 C9 7F cmp #$7f
001FF1 1 08 C9 7F D0 tst_a $7f,fzc
001FF5 1 FE 68 48 C9
001FF9 1 33 D0 FE 28
001FFD 1 A9 00 48 A9 set_a $7e,0
002001 1 7E 28
002003 1 C9 7F cmp #$7f
002005 1 08 C9 7E D0 tst_a $7e,fn
002009 1 FE 68 48 C9
00200D 1 B0 D0 FE 28
002011 1 A9 FF 48 A9 set_a $80,$ff
002015 1 80 28
002017 1 C9 7F cmp #$7f
002019 1 08 C9 80 D0 tst_a $80,~fnz
00201D 1 FE 68 48 C9
002021 1 7D D0 FE 28
002025 1 A9 FF 48 A9 set_a $7f,$ff
002029 1 7F 28
00202B 1 C9 7F cmp #$7f
00202D 1 08 C9 7F D0 tst_a $7f,~fn
002031 1 FE 68 48 C9
002035 1 7F D0 FE 28
002039 1 A9 FF 48 A9 set_a $7e,$ff
00203D 1 7E 28
00203F 1 C9 7F cmp #$7f
002041 1 08 C9 7E D0 tst_a $7e,~fzc
002045 1 FE 68 48 C9
002049 1 FC D0 FE 28
00204D 1
00204D 1 A2 04 ldx #4 ;with indexing by X
00204F 1 A9 00 48 A9 set_a $80,0
002053 1 80 28
002055 1 D5 15 cmp zp1,x
002057 1 08 C9 80 D0 tst_a $80,fc
00205B 1 FE 68 48 C9
00205F 1 31 D0 FE 28
002063 1 A9 00 48 A9 set_a $7f,0
002067 1 7F 28
002069 1 D5 15 cmp zp1,x
00206B 1 08 C9 7F D0 tst_a $7f,fzc
00206F 1 FE 68 48 C9
002073 1 33 D0 FE 28
002077 1 A9 00 48 A9 set_a $7e,0
00207B 1 7E 28
00207D 1 D5 15 cmp zp1,x
00207F 1 08 C9 7E D0 tst_a $7e,fn
002083 1 FE 68 48 C9
002087 1 B0 D0 FE 28
00208B 1 A9 FF 48 A9 set_a $80,$ff
00208F 1 80 28
002091 1 D5 15 cmp zp1,x
002093 1 08 C9 80 D0 tst_a $80,~fnz
002097 1 FE 68 48 C9
00209B 1 7D D0 FE 28
00209F 1 A9 FF 48 A9 set_a $7f,$ff
0020A3 1 7F 28
0020A5 1 D5 15 cmp zp1,x
0020A7 1 08 C9 7F D0 tst_a $7f,~fn
0020AB 1 FE 68 48 C9
0020AF 1 7F D0 FE 28
0020B3 1 A9 FF 48 A9 set_a $7e,$ff
0020B7 1 7E 28
0020B9 1 D5 15 cmp zp1,x
0020BB 1 08 C9 7E D0 tst_a $7e,~fzc
0020BF 1 FE 68 48 C9
0020C3 1 FC D0 FE 28
0020C7 1
0020C7 1 A9 00 48 A9 set_a $80,0
0020CB 1 80 28
0020CD 1 DD 18 02 cmp abs1,x
0020D0 1 08 C9 80 D0 tst_a $80,fc
0020D4 1 FE 68 48 C9
0020D8 1 31 D0 FE 28
0020DC 1 A9 00 48 A9 set_a $7f,0
0020E0 1 7F 28
0020E2 1 DD 18 02 cmp abs1,x
0020E5 1 08 C9 7F D0 tst_a $7f,fzc
0020E9 1 FE 68 48 C9
0020ED 1 33 D0 FE 28
0020F1 1 A9 00 48 A9 set_a $7e,0
0020F5 1 7E 28
0020F7 1 DD 18 02 cmp abs1,x
0020FA 1 08 C9 7E D0 tst_a $7e,fn
0020FE 1 FE 68 48 C9
002102 1 B0 D0 FE 28
002106 1 A9 FF 48 A9 set_a $80,$ff
00210A 1 80 28
00210C 1 DD 18 02 cmp abs1,x
00210F 1 08 C9 80 D0 tst_a $80,~fnz
002113 1 FE 68 48 C9
002117 1 7D D0 FE 28
00211B 1 A9 FF 48 A9 set_a $7f,$ff
00211F 1 7F 28
002121 1 DD 18 02 cmp abs1,x
002124 1 08 C9 7F D0 tst_a $7f,~fn
002128 1 FE 68 48 C9
00212C 1 7F D0 FE 28
002130 1 A9 FF 48 A9 set_a $7e,$ff
002134 1 7E 28
002136 1 DD 18 02 cmp abs1,x
002139 1 08 C9 7E D0 tst_a $7e,~fzc
00213D 1 FE 68 48 C9
002141 1 FC D0 FE 28
002145 1
002145 1 A0 04 ldy #4 ;with indexing by Y
002147 1 A2 08 ldx #8 ;with indexed indirect
002149 1 A9 00 48 A9 set_a $80,0
00214D 1 80 28
00214F 1 D9 18 02 cmp abs1,y
002152 1 08 C9 80 D0 tst_a $80,fc
002156 1 FE 68 48 C9
00215A 1 31 D0 FE 28
00215E 1 A9 00 48 A9 set_a $7f,0
002162 1 7F 28
002164 1 D9 18 02 cmp abs1,y
002167 1 08 C9 7F D0 tst_a $7f,fzc
00216B 1 FE 68 48 C9
00216F 1 33 D0 FE 28
002173 1 A9 00 48 A9 set_a $7e,0
002177 1 7E 28
002179 1 D9 18 02 cmp abs1,y
00217C 1 08 C9 7E D0 tst_a $7e,fn
002180 1 FE 68 48 C9
002184 1 B0 D0 FE 28
002188 1 A9 FF 48 A9 set_a $80,$ff
00218C 1 80 28
00218E 1 D9 18 02 cmp abs1,y
002191 1 08 C9 80 D0 tst_a $80,~fnz
002195 1 FE 68 48 C9
002199 1 7D D0 FE 28
00219D 1 A9 FF 48 A9 set_a $7f,$ff
0021A1 1 7F 28
0021A3 1 D9 18 02 cmp abs1,y
0021A6 1 08 C9 7F D0 tst_a $7f,~fn
0021AA 1 FE 68 48 C9
0021AE 1 7F D0 FE 28
0021B2 1 A9 FF 48 A9 set_a $7e,$ff
0021B6 1 7E 28
0021B8 1 D9 18 02 cmp abs1,y
0021BB 1 08 C9 7E D0 tst_a $7e,~fzc
0021BF 1 FE 68 48 C9
0021C3 1 FC D0 FE 28
0021C7 1
0021C7 1 A9 00 48 A9 set_a $80,0
0021CB 1 80 28
0021CD 1 C1 26 cmp (ind1,x)
0021CF 1 08 C9 80 D0 tst_a $80,fc
0021D3 1 FE 68 48 C9
0021D7 1 31 D0 FE 28
0021DB 1 A9 00 48 A9 set_a $7f,0
0021DF 1 7F 28
0021E1 1 C1 26 cmp (ind1,x)
0021E3 1 08 C9 7F D0 tst_a $7f,fzc
0021E7 1 FE 68 48 C9
0021EB 1 33 D0 FE 28
0021EF 1 A9 00 48 A9 set_a $7e,0
0021F3 1 7E 28
0021F5 1 C1 26 cmp (ind1,x)
0021F7 1 08 C9 7E D0 tst_a $7e,fn
0021FB 1 FE 68 48 C9
0021FF 1 B0 D0 FE 28
002203 1 A9 FF 48 A9 set_a $80,$ff
002207 1 80 28
002209 1 C1 26 cmp (ind1,x)
00220B 1 08 C9 80 D0 tst_a $80,~fnz
00220F 1 FE 68 48 C9
002213 1 7D D0 FE 28
002217 1 A9 FF 48 A9 set_a $7f,$ff
00221B 1 7F 28
00221D 1 C1 26 cmp (ind1,x)
00221F 1 08 C9 7F D0 tst_a $7f,~fn
002223 1 FE 68 48 C9
002227 1 7F D0 FE 28
00222B 1 A9 FF 48 A9 set_a $7e,$ff
00222F 1 7E 28
002231 1 C1 26 cmp (ind1,x)
002233 1 08 C9 7E D0 tst_a $7e,~fzc
002237 1 FE 68 48 C9
00223B 1 FC D0 FE 28
00223F 1
00223F 1 A9 00 48 A9 set_a $80,0
002243 1 80 28
002245 1 D1 26 cmp (ind1),y
002247 1 08 C9 80 D0 tst_a $80,fc
00224B 1 FE 68 48 C9
00224F 1 31 D0 FE 28
002253 1 A9 00 48 A9 set_a $7f,0
002257 1 7F 28
002259 1 D1 26 cmp (ind1),y
00225B 1 08 C9 7F D0 tst_a $7f,fzc
00225F 1 FE 68 48 C9
002263 1 33 D0 FE 28
002267 1 A9 00 48 A9 set_a $7e,0
00226B 1 7E 28
00226D 1 D1 26 cmp (ind1),y
00226F 1 08 C9 7E D0 tst_a $7e,fn
002273 1 FE 68 48 C9
002277 1 B0 D0 FE 28
00227B 1 A9 FF 48 A9 set_a $80,$ff
00227F 1 80 28
002281 1 D1 26 cmp (ind1),y
002283 1 08 C9 80 D0 tst_a $80,~fnz
002287 1 FE 68 48 C9
00228B 1 7D D0 FE 28
00228F 1 A9 FF 48 A9 set_a $7f,$ff
002293 1 7F 28
002295 1 D1 26 cmp (ind1),y
002297 1 08 C9 7F D0 tst_a $7f,~fn
00229B 1 FE 68 48 C9
00229F 1 7F D0 FE 28
0022A3 1 A9 FF 48 A9 set_a $7e,$ff
0022A7 1 7E 28
0022A9 1 D1 26 cmp (ind1),y
0022AB 1 08 C9 7E D0 tst_a $7e,~fzc
0022AF 1 FE 68 48 C9
0022B3 1 FC D0 FE 28
0022B7 1 AD 00 02 C9 next_test
0022BB 1 1C D0 FE A9
0022BF 1 1D 8D 00 02
0022C3 1
0022C3 1 ; testing shifts - ASL LSR ROL ROR all addressing modes
0022C3 1 ; shifts - accumulator
0022C3 1 A2 05 ldx #5
0022C5 1 tasl:
0022C5 1 A9 00 48 B5 set_ax zps,0
0022C9 1 13 28
0022CB 1 0A asl a
0022CC 1 08 DD 21 02 tst_ax rASL,fASL,0
0022D0 1 D0 FE 68 49
0022D4 1 30 DD 39 02
0022DA 1 CA dex
0022DB 1 10 E8 bpl tasl
0022DD 1 A2 05 ldx #5
0022DF 1 tasl1:
0022DF 1 A9 FF 48 B5 set_ax zps,$ff
0022E3 1 13 28
0022E5 1 0A asl a
0022E6 1 08 DD 21 02 tst_ax rASL,fASL,$ff-fnzc
0022EA 1 D0 FE 68 49
0022EE 1 7C DD 39 02
0022F4 1 CA dex
0022F5 1 10 E8 bpl tasl1
0022F7 1
0022F7 1 A2 05 ldx #5
0022F9 1 tlsr:
0022F9 1 A9 00 48 B5 set_ax zps,0
0022FD 1 13 28
0022FF 1 4A lsr a
002300 1 08 DD 2D 02 tst_ax rLSR,fLSR,0
002304 1 D0 FE 68 49
002308 1 30 DD 45 02
00230E 1 CA dex
00230F 1 10 E8 bpl tlsr
002311 1 A2 05 ldx #5
002313 1 tlsr1:
002313 1 A9 FF 48 B5 set_ax zps,$ff
002317 1 13 28
002319 1 4A lsr a
00231A 1 08 DD 2D 02 tst_ax rLSR,fLSR,$ff-fnzc
00231E 1 D0 FE 68 49
002322 1 7C DD 45 02
002328 1 CA dex
002329 1 10 E8 bpl tlsr1
00232B 1
00232B 1 A2 05 ldx #5
00232D 1 trol:
00232D 1 A9 00 48 B5 set_ax zps,0
002331 1 13 28
002333 1 2A rol a
002334 1 08 DD 21 02 tst_ax rROL,fROL,0
002338 1 D0 FE 68 49
00233C 1 30 DD 39 02
002342 1 CA dex
002343 1 10 E8 bpl trol
002345 1 A2 05 ldx #5
002347 1 trol1:
002347 1 A9 FE 48 B5 set_ax zps,$ff-fc
00234B 1 13 28
00234D 1 2A rol a
00234E 1 08 DD 21 02 tst_ax rROL,fROL,$ff-fnzc
002352 1 D0 FE 68 49
002356 1 7C DD 39 02
00235C 1 CA dex
00235D 1 10 E8 bpl trol1
00235F 1
00235F 1 A2 05 ldx #5
002361 1 trolc:
002361 1 A9 01 48 B5 set_ax zps,fc
002365 1 13 28
002367 1 2A rol a
002368 1 08 DD 27 02 tst_ax rROLc,fROLc,0
00236C 1 D0 FE 68 49
002370 1 30 DD 3F 02
002376 1 CA dex
002377 1 10 E8 bpl trolc
002379 1 A2 05 ldx #5
00237B 1 trolc1:
00237B 1 A9 FF 48 B5 set_ax zps,$ff
00237F 1 13 28
002381 1 2A rol a
002382 1 08 DD 27 02 tst_ax rROLc,fROLc,$ff-fnzc
002386 1 D0 FE 68 49
00238A 1 7C DD 3F 02
002390 1 CA dex
002391 1 10 E8 bpl trolc1
002393 1
002393 1 A2 05 ldx #5
002395 1 tror:
002395 1 A9 00 48 B5 set_ax zps,0
002399 1 13 28
00239B 1 6A ror a
00239C 1 08 DD 2D 02 tst_ax rROR,fROR,0
0023A0 1 D0 FE 68 49
0023A4 1 30 DD 45 02
0023AA 1 CA dex
0023AB 1 10 E8 bpl tror
0023AD 1 A2 05 ldx #5
0023AF 1 tror1:
0023AF 1 A9 FE 48 B5 set_ax zps,$ff-fc
0023B3 1 13 28
0023B5 1 6A ror a
0023B6 1 08 DD 2D 02 tst_ax rROR,fROR,$ff-fnzc
0023BA 1 D0 FE 68 49
0023BE 1 7C DD 45 02
0023C4 1 CA dex
0023C5 1 10 E8 bpl tror1
0023C7 1
0023C7 1 A2 05 ldx #5
0023C9 1 trorc:
0023C9 1 A9 01 48 B5 set_ax zps,fc
0023CD 1 13 28
0023CF 1 6A ror a
0023D0 1 08 DD 33 02 tst_ax rRORc,fRORc,0
0023D4 1 D0 FE 68 49
0023D8 1 30 DD 4B 02
0023DE 1 CA dex
0023DF 1 10 E8 bpl trorc
0023E1 1 A2 05 ldx #5
0023E3 1 trorc1:
0023E3 1 A9 FF 48 B5 set_ax zps,$ff
0023E7 1 13 28
0023E9 1 6A ror a
0023EA 1 08 DD 33 02 tst_ax rRORc,fRORc,$ff-fnzc
0023EE 1 D0 FE 68 49
0023F2 1 7C DD 4B 02
0023F8 1 CA dex
0023F9 1 10 E8 bpl trorc1
0023FB 1 AD 00 02 C9 next_test
0023FF 1 1D D0 FE A9
002403 1 1E 8D 00 02
002407 1
002407 1 ; shifts - zeropage
002407 1 A2 05 ldx #5
002409 1 tasl2:
002409 1 A9 00 48 B5 set_z zps,0
00240D 1 13 85 0C 28
002411 1 06 0C asl zpt
002413 1 08 A5 0C DD tst_z rASL,fASL,0
002417 1 21 02 D0 FE
00241B 1 68 49 30 DD
002423 1 CA dex
002424 1 10 E3 bpl tasl2
002426 1 A2 05 ldx #5
002428 1 tasl3:
002428 1 A9 FF 48 B5 set_z zps,$ff
00242C 1 13 85 0C 28
002430 1 06 0C asl zpt
002432 1 08 A5 0C DD tst_z rASL,fASL,$ff-fnzc
002436 1 21 02 D0 FE
00243A 1 68 49 7C DD
002442 1 CA dex
002443 1 10 E3 bpl tasl3
002445 1
002445 1 A2 05 ldx #5
002447 1 tlsr2:
002447 1 A9 00 48 B5 set_z zps,0
00244B 1 13 85 0C 28
00244F 1 46 0C lsr zpt
002451 1 08 A5 0C DD tst_z rLSR,fLSR,0
002455 1 2D 02 D0 FE
002459 1 68 49 30 DD
002461 1 CA dex
002462 1 10 E3 bpl tlsr2
002464 1 A2 05 ldx #5
002466 1 tlsr3:
002466 1 A9 FF 48 B5 set_z zps,$ff
00246A 1 13 85 0C 28
00246E 1 46 0C lsr zpt
002470 1 08 A5 0C DD tst_z rLSR,fLSR,$ff-fnzc
002474 1 2D 02 D0 FE
002478 1 68 49 7C DD
002480 1 CA dex
002481 1 10 E3 bpl tlsr3
002483 1
002483 1 A2 05 ldx #5
002485 1 trol2:
002485 1 A9 00 48 B5 set_z zps,0
002489 1 13 85 0C 28
00248D 1 26 0C rol zpt
00248F 1 08 A5 0C DD tst_z rROL,fROL,0
002493 1 21 02 D0 FE
002497 1 68 49 30 DD
00249F 1 CA dex
0024A0 1 10 E3 bpl trol2
0024A2 1 A2 05 ldx #5
0024A4 1 trol3:
0024A4 1 A9 FE 48 B5 set_z zps,$ff-fc
0024A8 1 13 85 0C 28
0024AC 1 26 0C rol zpt
0024AE 1 08 A5 0C DD tst_z rROL,fROL,$ff-fnzc
0024B2 1 21 02 D0 FE
0024B6 1 68 49 7C DD
0024BE 1 CA dex
0024BF 1 10 E3 bpl trol3
0024C1 1
0024C1 1 A2 05 ldx #5
0024C3 1 trolc2:
0024C3 1 A9 01 48 B5 set_z zps,fc
0024C7 1 13 85 0C 28
0024CB 1 26 0C rol zpt
0024CD 1 08 A5 0C DD tst_z rROLc,fROLc,0
0024D1 1 27 02 D0 FE
0024D5 1 68 49 30 DD
0024DD 1 CA dex
0024DE 1 10 E3 bpl trolc2
0024E0 1 A2 05 ldx #5
0024E2 1 trolc3:
0024E2 1 A9 FF 48 B5 set_z zps,$ff
0024E6 1 13 85 0C 28
0024EA 1 26 0C rol zpt
0024EC 1 08 A5 0C DD tst_z rROLc,fROLc,$ff-fnzc
0024F0 1 27 02 D0 FE
0024F4 1 68 49 7C DD
0024FC 1 CA dex
0024FD 1 10 E3 bpl trolc3
0024FF 1
0024FF 1 A2 05 ldx #5
002501 1 tror2:
002501 1 A9 00 48 B5 set_z zps,0
002505 1 13 85 0C 28
002509 1 66 0C ror zpt
00250B 1 08 A5 0C DD tst_z rROR,fROR,0
00250F 1 2D 02 D0 FE
002513 1 68 49 30 DD
00251B 1 CA dex
00251C 1 10 E3 bpl tror2
00251E 1 A2 05 ldx #5
002520 1 tror3:
002520 1 A9 FE 48 B5 set_z zps,$ff-fc
002524 1 13 85 0C 28
002528 1 66 0C ror zpt
00252A 1 08 A5 0C DD tst_z rROR,fROR,$ff-fnzc
00252E 1 2D 02 D0 FE
002532 1 68 49 7C DD
00253A 1 CA dex
00253B 1 10 E3 bpl tror3
00253D 1
00253D 1 A2 05 ldx #5
00253F 1 trorc2:
00253F 1 A9 01 48 B5 set_z zps,fc
002543 1 13 85 0C 28
002547 1 66 0C ror zpt
002549 1 08 A5 0C DD tst_z rRORc,fRORc,0
00254D 1 33 02 D0 FE
002551 1 68 49 30 DD
002559 1 CA dex
00255A 1 10 E3 bpl trorc2
00255C 1 A2 05 ldx #5
00255E 1 trorc3:
00255E 1 A9 FF 48 B5 set_z zps,$ff
002562 1 13 85 0C 28
002566 1 66 0C ror zpt
002568 1 08 A5 0C DD tst_z rRORc,fRORc,$ff-fnzc
00256C 1 33 02 D0 FE
002570 1 68 49 7C DD
002578 1 CA dex
002579 1 10 E3 bpl trorc3
00257B 1 AD 00 02 C9 next_test
00257F 1 1E D0 FE A9
002583 1 1F 8D 00 02
002587 1
002587 1 ; shifts - absolute
002587 1 A2 05 ldx #5
002589 1 tasl4:
002589 1 A9 00 48 B5 set_abs zps,0
00258D 1 13 8D 03 02
002591 1 28
002592 1 0E 03 02 asl abst
002595 1 08 AD 03 02 tst_abs rASL,fASL,0
002599 1 DD 21 02 D0
00259D 1 FE 68 49 30
0025A6 1 CA dex
0025A7 1 10 E0 bpl tasl4
0025A9 1 A2 05 ldx #5
0025AB 1 tasl5:
0025AB 1 A9 FF 48 B5 set_abs zps,$ff
0025AF 1 13 8D 03 02
0025B3 1 28
0025B4 1 0E 03 02 asl abst
0025B7 1 08 AD 03 02 tst_abs rASL,fASL,$ff-fnzc
0025BB 1 DD 21 02 D0
0025BF 1 FE 68 49 7C
0025C8 1 CA dex
0025C9 1 10 E0 bpl tasl5
0025CB 1
0025CB 1 A2 05 ldx #5
0025CD 1 tlsr4:
0025CD 1 A9 00 48 B5 set_abs zps,0
0025D1 1 13 8D 03 02
0025D5 1 28
0025D6 1 4E 03 02 lsr abst
0025D9 1 08 AD 03 02 tst_abs rLSR,fLSR,0
0025DD 1 DD 2D 02 D0
0025E1 1 FE 68 49 30
0025EA 1 CA dex
0025EB 1 10 E0 bpl tlsr4
0025ED 1 A2 05 ldx #5
0025EF 1 tlsr5:
0025EF 1 A9 FF 48 B5 set_abs zps,$ff
0025F3 1 13 8D 03 02
0025F7 1 28
0025F8 1 4E 03 02 lsr abst
0025FB 1 08 AD 03 02 tst_abs rLSR,fLSR,$ff-fnzc
0025FF 1 DD 2D 02 D0
002603 1 FE 68 49 7C
00260C 1 CA dex
00260D 1 10 E0 bpl tlsr5
00260F 1
00260F 1 A2 05 ldx #5
002611 1 trol4:
002611 1 A9 00 48 B5 set_abs zps,0
002615 1 13 8D 03 02
002619 1 28
00261A 1 2E 03 02 rol abst
00261D 1 08 AD 03 02 tst_abs rROL,fROL,0
002621 1 DD 21 02 D0
002625 1 FE 68 49 30
00262E 1 CA dex
00262F 1 10 E0 bpl trol4
002631 1 A2 05 ldx #5
002633 1 trol5:
002633 1 A9 FE 48 B5 set_abs zps,$ff-fc
002637 1 13 8D 03 02
00263B 1 28
00263C 1 2E 03 02 rol abst
00263F 1 08 AD 03 02 tst_abs rROL,fROL,$ff-fnzc
002643 1 DD 21 02 D0
002647 1 FE 68 49 7C
002650 1 CA dex
002651 1 10 E0 bpl trol5
002653 1
002653 1 A2 05 ldx #5
002655 1 trolc4:
002655 1 A9 01 48 B5 set_abs zps,fc
002659 1 13 8D 03 02
00265D 1 28
00265E 1 2E 03 02 rol abst
002661 1 08 AD 03 02 tst_abs rROLc,fROLc,0
002665 1 DD 27 02 D0
002669 1 FE 68 49 30
002672 1 CA dex
002673 1 10 E0 bpl trolc4
002675 1 A2 05 ldx #5
002677 1 trolc5:
002677 1 A9 FF 48 B5 set_abs zps,$ff
00267B 1 13 8D 03 02
00267F 1 28
002680 1 2E 03 02 rol abst
002683 1 08 AD 03 02 tst_abs rROLc,fROLc,$ff-fnzc
002687 1 DD 27 02 D0
00268B 1 FE 68 49 7C
002694 1 CA dex
002695 1 10 E0 bpl trolc5
002697 1
002697 1 A2 05 ldx #5
002699 1 tror4:
002699 1 A9 00 48 B5 set_abs zps,0
00269D 1 13 8D 03 02
0026A1 1 28
0026A2 1 6E 03 02 ror abst
0026A5 1 08 AD 03 02 tst_abs rROR,fROR,0
0026A9 1 DD 2D 02 D0
0026AD 1 FE 68 49 30
0026B6 1 CA dex
0026B7 1 10 E0 bpl tror4
0026B9 1 A2 05 ldx #5
0026BB 1 tror5:
0026BB 1 A9 FE 48 B5 set_abs zps,$ff-fc
0026BF 1 13 8D 03 02
0026C3 1 28
0026C4 1 6E 03 02 ror abst
0026C7 1 08 AD 03 02 tst_abs rROR,fROR,$ff-fnzc
0026CB 1 DD 2D 02 D0
0026CF 1 FE 68 49 7C
0026D8 1 CA dex
0026D9 1 10 E0 bpl tror5
0026DB 1
0026DB 1 A2 05 ldx #5
0026DD 1 trorc4:
0026DD 1 A9 01 48 B5 set_abs zps,fc
0026E1 1 13 8D 03 02
0026E5 1 28
0026E6 1 6E 03 02 ror abst
0026E9 1 08 AD 03 02 tst_abs rRORc,fRORc,0
0026ED 1 DD 33 02 D0
0026F1 1 FE 68 49 30
0026FA 1 CA dex
0026FB 1 10 E0 bpl trorc4
0026FD 1 A2 05 ldx #5
0026FF 1 trorc5:
0026FF 1 A9 FF 48 B5 set_abs zps,$ff
002703 1 13 8D 03 02
002707 1 28
002708 1 6E 03 02 ror abst
00270B 1 08 AD 03 02 tst_abs rRORc,fRORc,$ff-fnzc
00270F 1 DD 33 02 D0
002713 1 FE 68 49 7C
00271C 1 CA dex
00271D 1 10 E0 bpl trorc5
00271F 1 AD 00 02 C9 next_test
002723 1 1F D0 FE A9
002727 1 20 8D 00 02
00272B 1
00272B 1 ; shifts - zp indexed
00272B 1 A2 05 ldx #5
00272D 1 tasl6:
00272D 1 A9 00 48 B5 set_zx zps,0
002731 1 13 95 0C 28
002735 1 16 0C asl zpt,x
002737 1 08 B5 0C DD tst_zx rASL,fASL,0
00273B 1 21 02 D0 FE
00273F 1 68 49 30 DD
002747 1 CA dex
002748 1 10 E3 bpl tasl6
00274A 1 A2 05 ldx #5
00274C 1 tasl7:
00274C 1 A9 FF 48 B5 set_zx zps,$ff
002750 1 13 95 0C 28
002754 1 16 0C asl zpt,x
002756 1 08 B5 0C DD tst_zx rASL,fASL,$ff-fnzc
00275A 1 21 02 D0 FE
00275E 1 68 49 7C DD
002766 1 CA dex
002767 1 10 E3 bpl tasl7
002769 1
002769 1 A2 05 ldx #5
00276B 1 tlsr6:
00276B 1 A9 00 48 B5 set_zx zps,0
00276F 1 13 95 0C 28
002773 1 56 0C lsr zpt,x
002775 1 08 B5 0C DD tst_zx rLSR,fLSR,0
002779 1 2D 02 D0 FE
00277D 1 68 49 30 DD
002785 1 CA dex
002786 1 10 E3 bpl tlsr6
002788 1 A2 05 ldx #5
00278A 1 tlsr7:
00278A 1 A9 FF 48 B5 set_zx zps,$ff
00278E 1 13 95 0C 28
002792 1 56 0C lsr zpt,x
002794 1 08 B5 0C DD tst_zx rLSR,fLSR,$ff-fnzc
002798 1 2D 02 D0 FE
00279C 1 68 49 7C DD
0027A4 1 CA dex
0027A5 1 10 E3 bpl tlsr7
0027A7 1
0027A7 1 A2 05 ldx #5
0027A9 1 trol6:
0027A9 1 A9 00 48 B5 set_zx zps,0
0027AD 1 13 95 0C 28
0027B1 1 36 0C rol zpt,x
0027B3 1 08 B5 0C DD tst_zx rROL,fROL,0
0027B7 1 21 02 D0 FE
0027BB 1 68 49 30 DD
0027C3 1 CA dex
0027C4 1 10 E3 bpl trol6
0027C6 1 A2 05 ldx #5
0027C8 1 trol7:
0027C8 1 A9 FE 48 B5 set_zx zps,$ff-fc
0027CC 1 13 95 0C 28
0027D0 1 36 0C rol zpt,x
0027D2 1 08 B5 0C DD tst_zx rROL,fROL,$ff-fnzc
0027D6 1 21 02 D0 FE
0027DA 1 68 49 7C DD
0027E2 1 CA dex
0027E3 1 10 E3 bpl trol7
0027E5 1
0027E5 1 A2 05 ldx #5
0027E7 1 trolc6:
0027E7 1 A9 01 48 B5 set_zx zps,fc
0027EB 1 13 95 0C 28
0027EF 1 36 0C rol zpt,x
0027F1 1 08 B5 0C DD tst_zx rROLc,fROLc,0
0027F5 1 27 02 D0 FE
0027F9 1 68 49 30 DD
002801 1 CA dex
002802 1 10 E3 bpl trolc6
002804 1 A2 05 ldx #5
002806 1 trolc7:
002806 1 A9 FF 48 B5 set_zx zps,$ff
00280A 1 13 95 0C 28
00280E 1 36 0C rol zpt,x
002810 1 08 B5 0C DD tst_zx rROLc,fROLc,$ff-fnzc
002814 1 27 02 D0 FE
002818 1 68 49 7C DD
002820 1 CA dex
002821 1 10 E3 bpl trolc7
002823 1
002823 1 A2 05 ldx #5
002825 1 tror6:
002825 1 A9 00 48 B5 set_zx zps,0
002829 1 13 95 0C 28
00282D 1 76 0C ror zpt,x
00282F 1 08 B5 0C DD tst_zx rROR,fROR,0
002833 1 2D 02 D0 FE
002837 1 68 49 30 DD
00283F 1 CA dex
002840 1 10 E3 bpl tror6
002842 1 A2 05 ldx #5
002844 1 tror7:
002844 1 A9 FE 48 B5 set_zx zps,$ff-fc
002848 1 13 95 0C 28
00284C 1 76 0C ror zpt,x
00284E 1 08 B5 0C DD tst_zx rROR,fROR,$ff-fnzc
002852 1 2D 02 D0 FE
002856 1 68 49 7C DD
00285E 1 CA dex
00285F 1 10 E3 bpl tror7
002861 1
002861 1 A2 05 ldx #5
002863 1 trorc6:
002863 1 A9 01 48 B5 set_zx zps,fc
002867 1 13 95 0C 28
00286B 1 76 0C ror zpt,x
00286D 1 08 B5 0C DD tst_zx rRORc,fRORc,0
002871 1 33 02 D0 FE
002875 1 68 49 30 DD
00287D 1 CA dex
00287E 1 10 E3 bpl trorc6
002880 1 A2 05 ldx #5
002882 1 trorc7:
002882 1 A9 FF 48 B5 set_zx zps,$ff
002886 1 13 95 0C 28
00288A 1 76 0C ror zpt,x
00288C 1 08 B5 0C DD tst_zx rRORc,fRORc,$ff-fnzc
002890 1 33 02 D0 FE
002894 1 68 49 7C DD
00289C 1 CA dex
00289D 1 10 E3 bpl trorc7
00289F 1 AD 00 02 C9 next_test
0028A3 1 20 D0 FE A9
0028A7 1 21 8D 00 02
0028AB 1
0028AB 1 ; shifts - abs indexed
0028AB 1 A2 05 ldx #5
0028AD 1 tasl8:
0028AD 1 A9 00 48 B5 set_absx zps,0
0028B1 1 13 9D 03 02
0028B5 1 28
0028B6 1 1E 03 02 asl abst,x
0028B9 1 08 BD 03 02 tst_absx rASL,fASL,0
0028BD 1 DD 21 02 D0
0028C1 1 FE 68 49 30
0028CA 1 CA dex
0028CB 1 10 E0 bpl tasl8
0028CD 1 A2 05 ldx #5
0028CF 1 tasl9:
0028CF 1 A9 FF 48 B5 set_absx zps,$ff
0028D3 1 13 9D 03 02
0028D7 1 28
0028D8 1 1E 03 02 asl abst,x
0028DB 1 08 BD 03 02 tst_absx rASL,fASL,$ff-fnzc
0028DF 1 DD 21 02 D0
0028E3 1 FE 68 49 7C
0028EC 1 CA dex
0028ED 1 10 E0 bpl tasl9
0028EF 1
0028EF 1 A2 05 ldx #5
0028F1 1 tlsr8:
0028F1 1 A9 00 48 B5 set_absx zps,0
0028F5 1 13 9D 03 02
0028F9 1 28
0028FA 1 5E 03 02 lsr abst,x
0028FD 1 08 BD 03 02 tst_absx rLSR,fLSR,0
002901 1 DD 2D 02 D0
002905 1 FE 68 49 30
00290E 1 CA dex
00290F 1 10 E0 bpl tlsr8
002911 1 A2 05 ldx #5
002913 1 tlsr9:
002913 1 A9 FF 48 B5 set_absx zps,$ff
002917 1 13 9D 03 02
00291B 1 28
00291C 1 5E 03 02 lsr abst,x
00291F 1 08 BD 03 02 tst_absx rLSR,fLSR,$ff-fnzc
002923 1 DD 2D 02 D0
002927 1 FE 68 49 7C
002930 1 CA dex
002931 1 10 E0 bpl tlsr9
002933 1
002933 1 A2 05 ldx #5
002935 1 trol8:
002935 1 A9 00 48 B5 set_absx zps,0
002939 1 13 9D 03 02
00293D 1 28
00293E 1 3E 03 02 rol abst,x
002941 1 08 BD 03 02 tst_absx rROL,fROL,0
002945 1 DD 21 02 D0
002949 1 FE 68 49 30
002952 1 CA dex
002953 1 10 E0 bpl trol8
002955 1 A2 05 ldx #5
002957 1 trol9:
002957 1 A9 FE 48 B5 set_absx zps,$ff-fc
00295B 1 13 9D 03 02
00295F 1 28
002960 1 3E 03 02 rol abst,x
002963 1 08 BD 03 02 tst_absx rROL,fROL,$ff-fnzc
002967 1 DD 21 02 D0
00296B 1 FE 68 49 7C
002974 1 CA dex
002975 1 10 E0 bpl trol9
002977 1
002977 1 A2 05 ldx #5
002979 1 trolc8:
002979 1 A9 01 48 B5 set_absx zps,fc
00297D 1 13 9D 03 02
002981 1 28
002982 1 3E 03 02 rol abst,x
002985 1 08 BD 03 02 tst_absx rROLc,fROLc,0
002989 1 DD 27 02 D0
00298D 1 FE 68 49 30
002996 1 CA dex
002997 1 10 E0 bpl trolc8
002999 1 A2 05 ldx #5
00299B 1 trolc9:
00299B 1 A9 FF 48 B5 set_absx zps,$ff
00299F 1 13 9D 03 02
0029A3 1 28
0029A4 1 3E 03 02 rol abst,x
0029A7 1 08 BD 03 02 tst_absx rROLc,fROLc,$ff-fnzc
0029AB 1 DD 27 02 D0
0029AF 1 FE 68 49 7C
0029B8 1 CA dex
0029B9 1 10 E0 bpl trolc9
0029BB 1
0029BB 1 A2 05 ldx #5
0029BD 1 tror8:
0029BD 1 A9 00 48 B5 set_absx zps,0
0029C1 1 13 9D 03 02
0029C5 1 28
0029C6 1 7E 03 02 ror abst,x
0029C9 1 08 BD 03 02 tst_absx rROR,fROR,0
0029CD 1 DD 2D 02 D0
0029D1 1 FE 68 49 30
0029DA 1 CA dex
0029DB 1 10 E0 bpl tror8
0029DD 1 A2 05 ldx #5
0029DF 1 tror9:
0029DF 1 A9 FE 48 B5 set_absx zps,$ff-fc
0029E3 1 13 9D 03 02
0029E7 1 28
0029E8 1 7E 03 02 ror abst,x
0029EB 1 08 BD 03 02 tst_absx rROR,fROR,$ff-fnzc
0029EF 1 DD 2D 02 D0
0029F3 1 FE 68 49 7C
0029FC 1 CA dex
0029FD 1 10 E0 bpl tror9
0029FF 1
0029FF 1 A2 05 ldx #5
002A01 1 trorc8:
002A01 1 A9 01 48 B5 set_absx zps,fc
002A05 1 13 9D 03 02
002A09 1 28
002A0A 1 7E 03 02 ror abst,x
002A0D 1 08 BD 03 02 tst_absx rRORc,fRORc,0
002A11 1 DD 33 02 D0
002A15 1 FE 68 49 30
002A1E 1 CA dex
002A1F 1 10 E0 bpl trorc8
002A21 1 A2 05 ldx #5
002A23 1 trorc9:
002A23 1 A9 FF 48 B5 set_absx zps,$ff
002A27 1 13 9D 03 02
002A2B 1 28
002A2C 1 7E 03 02 ror abst,x
002A2F 1 08 BD 03 02 tst_absx rRORc,fRORc,$ff-fnzc
002A33 1 DD 33 02 D0
002A37 1 FE 68 49 7C
002A40 1 CA dex
002A41 1 10 E0 bpl trorc9
002A43 1 AD 00 02 C9 next_test
002A47 1 21 D0 FE A9
002A4B 1 22 8D 00 02
002A4F 1
002A4F 1 ; testing memory increment/decrement - INC DEC all addressing modes
002A4F 1 ; zeropage
002A4F 1 A2 00 ldx #0
002A51 1 A9 7E lda #$7e
002A53 1 85 0C sta zpt
002A55 1 tinc:
002A55 1 A9 00 48 28 set_stat 0
002A59 1 E6 0C inc zpt
002A5B 1 08 A5 0C DD tst_z rINC,fINC,0
002A5F 1 51 02 D0 FE
002A63 1 68 49 30 DD
002A6B 1 E8 inx
002A6C 1 E0 02 cpx #2
002A6E 1 D0 04 bne tinc1
002A70 1 A9 FE lda #$fe
002A72 1 85 0C sta zpt
002A74 1 E0 05 tinc1: cpx #5
002A76 1 D0 DD bne tinc
002A78 1 CA dex
002A79 1 E6 0C inc zpt
002A7B 1 tdec:
002A7B 1 A9 00 48 28 set_stat 0
002A7F 1 C6 0C dec zpt
002A81 1 08 A5 0C DD tst_z rINC,fINC,0
002A85 1 51 02 D0 FE
002A89 1 68 49 30 DD
002A91 1 CA dex
002A92 1 30 0A bmi tdec1
002A94 1 E0 01 cpx #1
002A96 1 D0 E3 bne tdec
002A98 1 A9 81 lda #$81
002A9A 1 85 0C sta zpt
002A9C 1 D0 DD bne tdec
002A9E 1 tdec1:
002A9E 1 A2 00 ldx #0
002AA0 1 A9 7E lda #$7e
002AA2 1 85 0C sta zpt
002AA4 1 tinc10:
002AA4 1 A9 FF 48 28 set_stat $ff
002AA8 1 E6 0C inc zpt
002AAA 1 08 A5 0C DD tst_z rINC,fINC,$ff-fnz
002AAE 1 51 02 D0 FE
002AB2 1 68 49 7D DD
002ABA 1 E8 inx
002ABB 1 E0 02 cpx #2
002ABD 1 D0 04 bne tinc11
002ABF 1 A9 FE lda #$fe
002AC1 1 85 0C sta zpt
002AC3 1 E0 05 tinc11: cpx #5
002AC5 1 D0 DD bne tinc10
002AC7 1 CA dex
002AC8 1 E6 0C inc zpt
002ACA 1 tdec10:
002ACA 1 A9 FF 48 28 set_stat $ff
002ACE 1 C6 0C dec zpt
002AD0 1 08 A5 0C DD tst_z rINC,fINC,$ff-fnz
002AD4 1 51 02 D0 FE
002AD8 1 68 49 7D DD
002AE0 1 CA dex
002AE1 1 30 0A bmi tdec11
002AE3 1 E0 01 cpx #1
002AE5 1 D0 E3 bne tdec10
002AE7 1 A9 81 lda #$81
002AE9 1 85 0C sta zpt
002AEB 1 D0 DD bne tdec10
002AED 1 tdec11:
002AED 1 AD 00 02 C9 next_test
002AF1 1 22 D0 FE A9
002AF5 1 23 8D 00 02
002AF9 1
002AF9 1 ; absolute memory
002AF9 1 A2 00 ldx #0
002AFB 1 A9 7E lda #$7e
002AFD 1 8D 03 02 sta abst
002B00 1 tinc2:
002B00 1 A9 00 48 28 set_stat 0
002B04 1 EE 03 02 inc abst
002B07 1 08 AD 03 02 tst_abs rINC,fINC,0
002B0B 1 DD 51 02 D0
002B0F 1 FE 68 49 30
002B18 1 E8 inx
002B19 1 E0 02 cpx #2
002B1B 1 D0 05 bne tinc3
002B1D 1 A9 FE lda #$fe
002B1F 1 8D 03 02 sta abst
002B22 1 E0 05 tinc3: cpx #5
002B24 1 D0 DA bne tinc2
002B26 1 CA dex
002B27 1 EE 03 02 inc abst
002B2A 1 tdec2:
002B2A 1 A9 00 48 28 set_stat 0
002B2E 1 CE 03 02 dec abst
002B31 1 08 AD 03 02 tst_abs rINC,fINC,0
002B35 1 DD 51 02 D0
002B39 1 FE 68 49 30
002B42 1 CA dex
002B43 1 30 0B bmi tdec3
002B45 1 E0 01 cpx #1
002B47 1 D0 E1 bne tdec2
002B49 1 A9 81 lda #$81
002B4B 1 8D 03 02 sta abst
002B4E 1 D0 DA bne tdec2
002B50 1 tdec3:
002B50 1 A2 00 ldx #0
002B52 1 A9 7E lda #$7e
002B54 1 8D 03 02 sta abst
002B57 1 tinc12:
002B57 1 A9 FF 48 28 set_stat $ff
002B5B 1 EE 03 02 inc abst
002B5E 1 08 AD 03 02 tst_abs rINC,fINC,$ff-fnz
002B62 1 DD 51 02 D0
002B66 1 FE 68 49 7D
002B6F 1 E8 inx
002B70 1 E0 02 cpx #2
002B72 1 D0 05 bne tinc13
002B74 1 A9 FE lda #$fe
002B76 1 8D 03 02 sta abst
002B79 1 E0 05 tinc13: cpx #5
002B7B 1 D0 DA bne tinc12
002B7D 1 CA dex
002B7E 1 EE 03 02 inc abst
002B81 1 tdec12:
002B81 1 A9 FF 48 28 set_stat $ff
002B85 1 CE 03 02 dec abst
002B88 1 08 AD 03 02 tst_abs rINC,fINC,$ff-fnz
002B8C 1 DD 51 02 D0
002B90 1 FE 68 49 7D
002B99 1 CA dex
002B9A 1 30 0B bmi tdec13
002B9C 1 E0 01 cpx #1
002B9E 1 D0 E1 bne tdec12
002BA0 1 A9 81 lda #$81
002BA2 1 8D 03 02 sta abst
002BA5 1 D0 DA bne tdec12
002BA7 1 tdec13:
002BA7 1 AD 00 02 C9 next_test
002BAB 1 23 D0 FE A9
002BAF 1 24 8D 00 02
002BB3 1
002BB3 1 ; zeropage indexed
002BB3 1 A2 00 ldx #0
002BB5 1 A9 7E lda #$7e
002BB7 1 95 0C tinc4: sta zpt,x
002BB9 1 A9 00 48 28 set_stat 0
002BBD 1 F6 0C inc zpt,x
002BBF 1 08 B5 0C DD tst_zx rINC,fINC,0
002BC3 1 51 02 D0 FE
002BC7 1 68 49 30 DD
002BCF 1 B5 0C lda zpt,x
002BD1 1 E8 inx
002BD2 1 E0 02 cpx #2
002BD4 1 D0 02 bne tinc5
002BD6 1 A9 FE lda #$fe
002BD8 1 E0 05 tinc5: cpx #5
002BDA 1 D0 DB bne tinc4
002BDC 1 CA dex
002BDD 1 A9 02 lda #2
002BDF 1 95 0C tdec4: sta zpt,x
002BE1 1 A9 00 48 28 set_stat 0
002BE5 1 D6 0C dec zpt,x
002BE7 1 08 B5 0C DD tst_zx rINC,fINC,0
002BEB 1 51 02 D0 FE
002BEF 1 68 49 30 DD
002BF7 1 B5 0C lda zpt,x
002BF9 1 CA dex
002BFA 1 30 08 bmi tdec5
002BFC 1 E0 01 cpx #1
002BFE 1 D0 DF bne tdec4
002C00 1 A9 81 lda #$81
002C02 1 D0 DB bne tdec4
002C04 1 tdec5:
002C04 1 A2 00 ldx #0
002C06 1 A9 7E lda #$7e
002C08 1 95 0C tinc14: sta zpt,x
002C0A 1 A9 FF 48 28 set_stat $ff
002C0E 1 F6 0C inc zpt,x
002C10 1 08 B5 0C DD tst_zx rINC,fINC,$ff-fnz
002C14 1 51 02 D0 FE
002C18 1 68 49 7D DD
002C20 1 B5 0C lda zpt,x
002C22 1 E8 inx
002C23 1 E0 02 cpx #2
002C25 1 D0 02 bne tinc15
002C27 1 A9 FE lda #$fe
002C29 1 E0 05 tinc15: cpx #5
002C2B 1 D0 DB bne tinc14
002C2D 1 CA dex
002C2E 1 A9 02 lda #2
002C30 1 95 0C tdec14: sta zpt,x
002C32 1 A9 FF 48 28 set_stat $ff
002C36 1 D6 0C dec zpt,x
002C38 1 08 B5 0C DD tst_zx rINC,fINC,$ff-fnz
002C3C 1 51 02 D0 FE
002C40 1 68 49 7D DD
002C48 1 B5 0C lda zpt,x
002C4A 1 CA dex
002C4B 1 30 08 bmi tdec15
002C4D 1 E0 01 cpx #1
002C4F 1 D0 DF bne tdec14
002C51 1 A9 81 lda #$81
002C53 1 D0 DB bne tdec14
002C55 1 tdec15:
002C55 1 AD 00 02 C9 next_test
002C59 1 24 D0 FE A9
002C5D 1 25 8D 00 02
002C61 1
002C61 1 ; memory indexed
002C61 1 A2 00 ldx #0
002C63 1 A9 7E lda #$7e
002C65 1 9D 03 02 tinc6: sta abst,x
002C68 1 A9 00 48 28 set_stat 0
002C6C 1 FE 03 02 inc abst,x
002C6F 1 08 BD 03 02 tst_absx rINC,fINC,0
002C73 1 DD 51 02 D0
002C77 1 FE 68 49 30
002C80 1 BD 03 02 lda abst,x
002C83 1 E8 inx
002C84 1 E0 02 cpx #2
002C86 1 D0 02 bne tinc7
002C88 1 A9 FE lda #$fe
002C8A 1 E0 05 tinc7: cpx #5
002C8C 1 D0 D7 bne tinc6
002C8E 1 CA dex
002C8F 1 A9 02 lda #2
002C91 1 9D 03 02 tdec6: sta abst,x
002C94 1 A9 00 48 28 set_stat 0
002C98 1 DE 03 02 dec abst,x
002C9B 1 08 BD 03 02 tst_absx rINC,fINC,0
002C9F 1 DD 51 02 D0
002CA3 1 FE 68 49 30
002CAC 1 BD 03 02 lda abst,x
002CAF 1 CA dex
002CB0 1 30 08 bmi tdec7
002CB2 1 E0 01 cpx #1
002CB4 1 D0 DB bne tdec6
002CB6 1 A9 81 lda #$81
002CB8 1 D0 D7 bne tdec6
002CBA 1 tdec7:
002CBA 1 A2 00 ldx #0
002CBC 1 A9 7E lda #$7e
002CBE 1 9D 03 02 tinc16: sta abst,x
002CC1 1 A9 FF 48 28 set_stat $ff
002CC5 1 FE 03 02 inc abst,x
002CC8 1 08 BD 03 02 tst_absx rINC,fINC,$ff-fnz
002CCC 1 DD 51 02 D0
002CD0 1 FE 68 49 7D
002CD9 1 BD 03 02 lda abst,x
002CDC 1 E8 inx
002CDD 1 E0 02 cpx #2
002CDF 1 D0 02 bne tinc17
002CE1 1 A9 FE lda #$fe
002CE3 1 E0 05 tinc17: cpx #5
002CE5 1 D0 D7 bne tinc16
002CE7 1 CA dex
002CE8 1 A9 02 lda #2
002CEA 1 9D 03 02 tdec16: sta abst,x
002CED 1 A9 FF 48 28 set_stat $ff
002CF1 1 DE 03 02 dec abst,x
002CF4 1 08 BD 03 02 tst_absx rINC,fINC,$ff-fnz
002CF8 1 DD 51 02 D0
002CFC 1 FE 68 49 7D
002D05 1 BD 03 02 lda abst,x
002D08 1 CA dex
002D09 1 30 08 bmi tdec17
002D0B 1 E0 01 cpx #1
002D0D 1 D0 DB bne tdec16
002D0F 1 A9 81 lda #$81
002D11 1 D0 D7 bne tdec16
002D13 1 tdec17:
002D13 1 AD 00 02 C9 next_test
002D17 1 25 D0 FE A9
002D1B 1 26 8D 00 02
002D1F 1
002D1F 1 ; testing logical instructions - AND EOR ORA all addressing modes
002D1F 1 ; AND
002D1F 1 A2 03 ldx #3 ;immediate
002D21 1 B5 1E tand: lda zpAN,x
002D23 1 8D 0A 02 sta ex_andi+1 ;set AND # operand
002D26 1 A9 00 48 BD set_ax absANa,0
002D2A 1 6B 02 28
002D2D 1 20 09 02 jsr ex_andi ;execute AND # in RAM
002D30 1 08 DD 73 02 tst_ax absrlo,absflo,0
002D34 1 D0 FE 68 49
002D38 1 30 DD 77 02
002D3E 1 CA dex
002D3F 1 10 E0 bpl tand
002D41 1 A2 03 ldx #3
002D43 1 B5 1E tand1: lda zpAN,x
002D45 1 8D 0A 02 sta ex_andi+1 ;set AND # operand
002D48 1 A9 FF 48 BD set_ax absANa,$ff
002D4C 1 6B 02 28
002D4F 1 20 09 02 jsr ex_andi ;execute AND # in RAM
002D52 1 08 DD 73 02 tst_ax absrlo,absflo,$ff-fnz
002D56 1 D0 FE 68 49
002D5A 1 7D DD 77 02
002D60 1 CA dex
002D61 1 10 E0 bpl tand1
002D63 1
002D63 1 A2 03 ldx #3 ;zp
002D65 1 B5 1E tand2: lda zpAN,x
002D67 1 85 0C sta zpt
002D69 1 A9 00 48 BD set_ax absANa,0
002D6D 1 6B 02 28
002D70 1 25 0C and zpt
002D72 1 08 DD 73 02 tst_ax absrlo,absflo,0
002D76 1 D0 FE 68 49
002D7A 1 30 DD 77 02
002D80 1 CA dex
002D81 1 10 E2 bpl tand2
002D83 1 A2 03 ldx #3
002D85 1 B5 1E tand3: lda zpAN,x
002D87 1 85 0C sta zpt
002D89 1 A9 FF 48 BD set_ax absANa,$ff
002D8D 1 6B 02 28
002D90 1 25 0C and zpt
002D92 1 08 DD 73 02 tst_ax absrlo,absflo,$ff-fnz
002D96 1 D0 FE 68 49
002D9A 1 7D DD 77 02
002DA0 1 CA dex
002DA1 1 10 E2 bpl tand3
002DA3 1
002DA3 1 A2 03 ldx #3 ;abs
002DA5 1 B5 1E tand4: lda zpAN,x
002DA7 1 8D 03 02 sta abst
002DAA 1 A9 00 48 BD set_ax absANa,0
002DAE 1 6B 02 28
002DB1 1 2D 03 02 and abst
002DB4 1 08 DD 73 02 tst_ax absrlo,absflo,0
002DB8 1 D0 FE 68 49
002DBC 1 30 DD 77 02
002DC2 1 CA dex
002DC3 1 10 E0 bpl tand4
002DC5 1 A2 03 ldx #3
002DC7 1 B5 1E tand5: lda zpAN,x
002DC9 1 8D 03 02 sta abst
002DCC 1 A9 FF 48 BD set_ax absANa,$ff
002DD0 1 6B 02 28
002DD3 1 2D 03 02 and abst
002DD6 1 08 DD 73 02 tst_ax absrlo,absflo,$ff-fnz
002DDA 1 D0 FE 68 49
002DDE 1 7D DD 77 02
002DE4 1 CA dex
002DE5 1 10 02 bpl tand6
002DE7 1
002DE7 1 A2 03 ldx #3 ;zp,x
002DE9 1 tand6:
002DE9 1 A9 00 48 BD set_ax absANa,0
002DED 1 6B 02 28
002DF0 1 35 1E and zpAN,x
002DF2 1 08 DD 73 02 tst_ax absrlo,absflo,0
002DF6 1 D0 FE 68 49
002DFA 1 30 DD 77 02
002E00 1 CA dex
002E01 1 10 E6 bpl tand6
002E03 1 A2 03 ldx #3
002E05 1 tand7:
002E05 1 A9 FF 48 BD set_ax absANa,$ff
002E09 1 6B 02 28
002E0C 1 35 1E and zpAN,x
002E0E 1 08 DD 73 02 tst_ax absrlo,absflo,$ff-fnz
002E12 1 D0 FE 68 49
002E16 1 7D DD 77 02
002E1C 1 CA dex
002E1D 1 10 E6 bpl tand7
002E1F 1
002E1F 1 A2 03 ldx #3 ;abs,x
002E21 1 tand8:
002E21 1 A9 00 48 BD set_ax absANa,0
002E25 1 6B 02 28
002E28 1 3D 5F 02 and absAN,x
002E2B 1 08 DD 73 02 tst_ax absrlo,absflo,0
002E2F 1 D0 FE 68 49
002E33 1 30 DD 77 02
002E39 1 CA dex
002E3A 1 10 E5 bpl tand8
002E3C 1 A2 03 ldx #3
002E3E 1 tand9:
002E3E 1 A9 FF 48 BD set_ax absANa,$ff
002E42 1 6B 02 28
002E45 1 3D 5F 02 and absAN,x
002E48 1 08 DD 73 02 tst_ax absrlo,absflo,$ff-fnz
002E4C 1 D0 FE 68 49
002E50 1 7D DD 77 02
002E56 1 CA dex
002E57 1 10 E5 bpl tand9
002E59 1
002E59 1 A0 03 ldy #3 ;abs,y
002E5B 1 tand10:
002E5B 1 A9 00 48 B9 set_ay absANa,0
002E5F 1 6B 02 28
002E62 1 39 5F 02 and absAN,y
002E65 1 08 D9 73 02 tst_ay absrlo,absflo,0
002E69 1 D0 FE 68 49
002E6D 1 30 D9 77 02
002E73 1 88 dey
002E74 1 10 E5 bpl tand10
002E76 1 A0 03 ldy #3
002E78 1 tand11:
002E78 1 A9 FF 48 B9 set_ay absANa,$ff
002E7C 1 6B 02 28
002E7F 1 39 5F 02 and absAN,y
002E82 1 08 D9 73 02 tst_ay absrlo,absflo,$ff-fnz
002E86 1 D0 FE 68 49
002E8A 1 7D D9 77 02
002E90 1 88 dey
002E91 1 10 E5 bpl tand11
002E93 1
002E93 1 A2 06 ldx #6 ;(zp,x)
002E95 1 A0 03 ldy #3
002E97 1 tand12:
002E97 1 A9 00 48 B9 set_ay absANa,0
002E9B 1 6B 02 28
002E9E 1 21 3C and (indAN,x)
002EA0 1 08 D9 73 02 tst_ay absrlo,absflo,0
002EA4 1 D0 FE 68 49
002EA8 1 30 D9 77 02
002EAE 1 CA dex
002EAF 1 CA dex
002EB0 1 88 dey
002EB1 1 10 E4 bpl tand12
002EB3 1 A2 06 ldx #6
002EB5 1 A0 03 ldy #3
002EB7 1 tand13:
002EB7 1 A9 FF 48 B9 set_ay absANa,$ff
002EBB 1 6B 02 28
002EBE 1 21 3C and (indAN,x)
002EC0 1 08 D9 73 02 tst_ay absrlo,absflo,$ff-fnz
002EC4 1 D0 FE 68 49
002EC8 1 7D D9 77 02
002ECE 1 CA dex
002ECF 1 CA dex
002ED0 1 88 dey
002ED1 1 10 E4 bpl tand13
002ED3 1
002ED3 1 A0 03 ldy #3 ;(zp),y
002ED5 1 tand14:
002ED5 1 A9 00 48 B9 set_ay absANa,0
002ED9 1 6B 02 28
002EDC 1 31 3C and (indAN),y
002EDE 1 08 D9 73 02 tst_ay absrlo,absflo,0
002EE2 1 D0 FE 68 49
002EE6 1 30 D9 77 02
002EEC 1 88 dey
002EED 1 10 E6 bpl tand14
002EEF 1 A0 03 ldy #3
002EF1 1 tand15:
002EF1 1 A9 FF 48 B9 set_ay absANa,$ff
002EF5 1 6B 02 28
002EF8 1 31 3C and (indAN),y
002EFA 1 08 D9 73 02 tst_ay absrlo,absflo,$ff-fnz
002EFE 1 D0 FE 68 49
002F02 1 7D D9 77 02
002F08 1 88 dey
002F09 1 10 E6 bpl tand15
002F0B 1 AD 00 02 C9 next_test
002F0F 1 26 D0 FE A9
002F13 1 27 8D 00 02
002F17 1
002F17 1 ; EOR
002F17 1 A2 03 ldx #3 ;immediate - self modifying code
002F19 1 B5 22 teor: lda zpEO,x
002F1B 1 8D 0D 02 sta ex_eori+1 ;set EOR # operand
002F1E 1 A9 00 48 BD set_ax absEOa,0
002F22 1 6F 02 28
002F25 1 20 0C 02 jsr ex_eori ;execute EOR # in RAM
002F28 1 08 DD 73 02 tst_ax absrlo,absflo,0
002F2C 1 D0 FE 68 49
002F30 1 30 DD 77 02
002F36 1 CA dex
002F37 1 10 E0 bpl teor
002F39 1 A2 03 ldx #3
002F3B 1 B5 22 teor1: lda zpEO,x
002F3D 1 8D 0D 02 sta ex_eori+1 ;set EOR # operand
002F40 1 A9 FF 48 BD set_ax absEOa,$ff
002F44 1 6F 02 28
002F47 1 20 0C 02 jsr ex_eori ;execute EOR # in RAM
002F4A 1 08 DD 73 02 tst_ax absrlo,absflo,$ff-fnz
002F4E 1 D0 FE 68 49
002F52 1 7D DD 77 02
002F58 1 CA dex
002F59 1 10 E0 bpl teor1
002F5B 1
002F5B 1 A2 03 ldx #3 ;zp
002F5D 1 B5 22 teor2: lda zpEO,x
002F5F 1 85 0C sta zpt
002F61 1 A9 00 48 BD set_ax absEOa,0
002F65 1 6F 02 28
002F68 1 45 0C eor zpt
002F6A 1 08 DD 73 02 tst_ax absrlo,absflo,0
002F6E 1 D0 FE 68 49
002F72 1 30 DD 77 02
002F78 1 CA dex
002F79 1 10 E2 bpl teor2
002F7B 1 A2 03 ldx #3
002F7D 1 B5 22 teor3: lda zpEO,x
002F7F 1 85 0C sta zpt
002F81 1 A9 FF 48 BD set_ax absEOa,$ff
002F85 1 6F 02 28
002F88 1 45 0C eor zpt
002F8A 1 08 DD 73 02 tst_ax absrlo,absflo,$ff-fnz
002F8E 1 D0 FE 68 49
002F92 1 7D DD 77 02
002F98 1 CA dex
002F99 1 10 E2 bpl teor3
002F9B 1
002F9B 1 A2 03 ldx #3 ;abs
002F9D 1 B5 22 teor4: lda zpEO,x
002F9F 1 8D 03 02 sta abst
002FA2 1 A9 00 48 BD set_ax absEOa,0
002FA6 1 6F 02 28
002FA9 1 4D 03 02 eor abst
002FAC 1 08 DD 73 02 tst_ax absrlo,absflo,0
002FB0 1 D0 FE 68 49
002FB4 1 30 DD 77 02
002FBA 1 CA dex
002FBB 1 10 E0 bpl teor4
002FBD 1 A2 03 ldx #3
002FBF 1 B5 22 teor5: lda zpEO,x
002FC1 1 8D 03 02 sta abst
002FC4 1 A9 FF 48 BD set_ax absEOa,$ff
002FC8 1 6F 02 28
002FCB 1 4D 03 02 eor abst
002FCE 1 08 DD 73 02 tst_ax absrlo,absflo,$ff-fnz
002FD2 1 D0 FE 68 49
002FD6 1 7D DD 77 02
002FDC 1 CA dex
002FDD 1 10 02 bpl teor6
002FDF 1
002FDF 1 A2 03 ldx #3 ;zp,x
002FE1 1 teor6:
002FE1 1 A9 00 48 BD set_ax absEOa,0
002FE5 1 6F 02 28
002FE8 1 55 22 eor zpEO,x
002FEA 1 08 DD 73 02 tst_ax absrlo,absflo,0
002FEE 1 D0 FE 68 49
002FF2 1 30 DD 77 02
002FF8 1 CA dex
002FF9 1 10 E6 bpl teor6
002FFB 1 A2 03 ldx #3
002FFD 1 teor7:
002FFD 1 A9 FF 48 BD set_ax absEOa,$ff
003001 1 6F 02 28
003004 1 55 22 eor zpEO,x
003006 1 08 DD 73 02 tst_ax absrlo,absflo,$ff-fnz
00300A 1 D0 FE 68 49
00300E 1 7D DD 77 02
003014 1 CA dex
003015 1 10 E6 bpl teor7
003017 1
003017 1 A2 03 ldx #3 ;abs,x
003019 1 teor8:
003019 1 A9 00 48 BD set_ax absEOa,0
00301D 1 6F 02 28
003020 1 5D 63 02 eor absEO,x
003023 1 08 DD 73 02 tst_ax absrlo,absflo,0
003027 1 D0 FE 68 49
00302B 1 30 DD 77 02
003031 1 CA dex
003032 1 10 E5 bpl teor8
003034 1 A2 03 ldx #3
003036 1 teor9:
003036 1 A9 FF 48 BD set_ax absEOa,$ff
00303A 1 6F 02 28
00303D 1 5D 63 02 eor absEO,x
003040 1 08 DD 73 02 tst_ax absrlo,absflo,$ff-fnz
003044 1 D0 FE 68 49
003048 1 7D DD 77 02
00304E 1 CA dex
00304F 1 10 E5 bpl teor9
003051 1
003051 1 A0 03 ldy #3 ;abs,y
003053 1 teor10:
003053 1 A9 00 48 B9 set_ay absEOa,0
003057 1 6F 02 28
00305A 1 59 63 02 eor absEO,y
00305D 1 08 D9 73 02 tst_ay absrlo,absflo,0
003061 1 D0 FE 68 49
003065 1 30 D9 77 02
00306B 1 88 dey
00306C 1 10 E5 bpl teor10
00306E 1 A0 03 ldy #3
003070 1 teor11:
003070 1 A9 FF 48 B9 set_ay absEOa,$ff
003074 1 6F 02 28
003077 1 59 63 02 eor absEO,y
00307A 1 08 D9 73 02 tst_ay absrlo,absflo,$ff-fnz
00307E 1 D0 FE 68 49
003082 1 7D D9 77 02
003088 1 88 dey
003089 1 10 E5 bpl teor11
00308B 1
00308B 1 A2 06 ldx #6 ;(zp,x)
00308D 1 A0 03 ldy #3
00308F 1 teor12:
00308F 1 A9 00 48 B9 set_ay absEOa,0
003093 1 6F 02 28
003096 1 41 44 eor (indEO,x)
003098 1 08 D9 73 02 tst_ay absrlo,absflo,0
00309C 1 D0 FE 68 49
0030A0 1 30 D9 77 02
0030A6 1 CA dex
0030A7 1 CA dex
0030A8 1 88 dey
0030A9 1 10 E4 bpl teor12
0030AB 1 A2 06 ldx #6
0030AD 1 A0 03 ldy #3
0030AF 1 teor13:
0030AF 1 A9 FF 48 B9 set_ay absEOa,$ff
0030B3 1 6F 02 28
0030B6 1 41 44 eor (indEO,x)
0030B8 1 08 D9 73 02 tst_ay absrlo,absflo,$ff-fnz
0030BC 1 D0 FE 68 49
0030C0 1 7D D9 77 02
0030C6 1 CA dex
0030C7 1 CA dex
0030C8 1 88 dey
0030C9 1 10 E4 bpl teor13
0030CB 1
0030CB 1 A0 03 ldy #3 ;(zp),y
0030CD 1 teor14:
0030CD 1 A9 00 48 B9 set_ay absEOa,0
0030D1 1 6F 02 28
0030D4 1 51 44 eor (indEO),y
0030D6 1 08 D9 73 02 tst_ay absrlo,absflo,0
0030DA 1 D0 FE 68 49
0030DE 1 30 D9 77 02
0030E4 1 88 dey
0030E5 1 10 E6 bpl teor14
0030E7 1 A0 03 ldy #3
0030E9 1 teor15:
0030E9 1 A9 FF 48 B9 set_ay absEOa,$ff
0030ED 1 6F 02 28
0030F0 1 51 44 eor (indEO),y
0030F2 1 08 D9 73 02 tst_ay absrlo,absflo,$ff-fnz
0030F6 1 D0 FE 68 49
0030FA 1 7D D9 77 02
003100 1 88 dey
003101 1 10 E6 bpl teor15
003103 1 AD 00 02 C9 next_test
003107 1 27 D0 FE A9
00310B 1 28 8D 00 02
00310F 1
00310F 1 ; OR
00310F 1 A2 03 ldx #3 ;immediate - self modifying code
003111 1 B5 1A tora: lda zpOR,x
003113 1 8D 10 02 sta ex_orai+1 ;set ORA # operand
003116 1 A9 00 48 BD set_ax absORa,0
00311A 1 67 02 28
00311D 1 20 0F 02 jsr ex_orai ;execute ORA # in RAM
003120 1 08 DD 73 02 tst_ax absrlo,absflo,0
003124 1 D0 FE 68 49
003128 1 30 DD 77 02
00312E 1 CA dex
00312F 1 10 E0 bpl tora
003131 1 A2 03 ldx #3
003133 1 B5 1A tora1: lda zpOR,x
003135 1 8D 10 02 sta ex_orai+1 ;set ORA # operand
003138 1 A9 FF 48 BD set_ax absORa,$ff
00313C 1 67 02 28
00313F 1 20 0F 02 jsr ex_orai ;execute ORA # in RAM
003142 1 08 DD 73 02 tst_ax absrlo,absflo,$ff-fnz
003146 1 D0 FE 68 49
00314A 1 7D DD 77 02
003150 1 CA dex
003151 1 10 E0 bpl tora1
003153 1
003153 1 A2 03 ldx #3 ;zp
003155 1 B5 1A tora2: lda zpOR,x
003157 1 85 0C sta zpt
003159 1 A9 00 48 BD set_ax absORa,0
00315D 1 67 02 28
003160 1 05 0C ora zpt
003162 1 08 DD 73 02 tst_ax absrlo,absflo,0
003166 1 D0 FE 68 49
00316A 1 30 DD 77 02
003170 1 CA dex
003171 1 10 E2 bpl tora2
003173 1 A2 03 ldx #3
003175 1 B5 1A tora3: lda zpOR,x
003177 1 85 0C sta zpt
003179 1 A9 FF 48 BD set_ax absORa,$ff
00317D 1 67 02 28
003180 1 05 0C ora zpt
003182 1 08 DD 73 02 tst_ax absrlo,absflo,$ff-fnz
003186 1 D0 FE 68 49
00318A 1 7D DD 77 02
003190 1 CA dex
003191 1 10 E2 bpl tora3
003193 1
003193 1 A2 03 ldx #3 ;abs
003195 1 B5 1A tora4: lda zpOR,x
003197 1 8D 03 02 sta abst
00319A 1 A9 00 48 BD set_ax absORa,0
00319E 1 67 02 28
0031A1 1 0D 03 02 ora abst
0031A4 1 08 DD 73 02 tst_ax absrlo,absflo,0
0031A8 1 D0 FE 68 49
0031AC 1 30 DD 77 02
0031B2 1 CA dex
0031B3 1 10 E0 bpl tora4
0031B5 1 A2 03 ldx #3
0031B7 1 B5 1A tora5: lda zpOR,x
0031B9 1 8D 03 02 sta abst
0031BC 1 A9 FF 48 BD set_ax absORa,$ff
0031C0 1 67 02 28
0031C3 1 0D 03 02 ora abst
0031C6 1 08 DD 73 02 tst_ax absrlo,absflo,$ff-fnz
0031CA 1 D0 FE 68 49
0031CE 1 7D DD 77 02
0031D4 1 CA dex
0031D5 1 10 02 bpl tora6
0031D7 1
0031D7 1 A2 03 ldx #3 ;zp,x
0031D9 1 tora6:
0031D9 1 A9 00 48 BD set_ax absORa,0
0031DD 1 67 02 28
0031E0 1 15 1A ora zpOR,x
0031E2 1 08 DD 73 02 tst_ax absrlo,absflo,0
0031E6 1 D0 FE 68 49
0031EA 1 30 DD 77 02
0031F0 1 CA dex
0031F1 1 10 E6 bpl tora6
0031F3 1 A2 03 ldx #3
0031F5 1 tora7:
0031F5 1 A9 FF 48 BD set_ax absORa,$ff
0031F9 1 67 02 28
0031FC 1 15 1A ora zpOR,x
0031FE 1 08 DD 73 02 tst_ax absrlo,absflo,$ff-fnz
003202 1 D0 FE 68 49
003206 1 7D DD 77 02
00320C 1 CA dex
00320D 1 10 E6 bpl tora7
00320F 1
00320F 1 A2 03 ldx #3 ;abs,x
003211 1 tora8:
003211 1 A9 00 48 BD set_ax absORa,0
003215 1 67 02 28
003218 1 1D 5B 02 ora absOR,x
00321B 1 08 DD 73 02 tst_ax absrlo,absflo,0
00321F 1 D0 FE 68 49
003223 1 30 DD 77 02
003229 1 CA dex
00322A 1 10 E5 bpl tora8
00322C 1 A2 03 ldx #3
00322E 1 tora9:
00322E 1 A9 FF 48 BD set_ax absORa,$ff
003232 1 67 02 28
003235 1 1D 5B 02 ora absOR,x
003238 1 08 DD 73 02 tst_ax absrlo,absflo,$ff-fnz
00323C 1 D0 FE 68 49
003240 1 7D DD 77 02
003246 1 CA dex
003247 1 10 E5 bpl tora9
003249 1
003249 1 A0 03 ldy #3 ;abs,y
00324B 1 tora10:
00324B 1 A9 00 48 B9 set_ay absORa,0
00324F 1 67 02 28
003252 1 19 5B 02 ora absOR,y
003255 1 08 D9 73 02 tst_ay absrlo,absflo,0
003259 1 D0 FE 68 49
00325D 1 30 D9 77 02
003263 1 88 dey
003264 1 10 E5 bpl tora10
003266 1 A0 03 ldy #3
003268 1 tora11:
003268 1 A9 FF 48 B9 set_ay absORa,$ff
00326C 1 67 02 28
00326F 1 19 5B 02 ora absOR,y
003272 1 08 D9 73 02 tst_ay absrlo,absflo,$ff-fnz
003276 1 D0 FE 68 49
00327A 1 7D D9 77 02
003280 1 88 dey
003281 1 10 E5 bpl tora11
003283 1
003283 1 A2 06 ldx #6 ;(zp,x)
003285 1 A0 03 ldy #3
003287 1 tora12:
003287 1 A9 00 48 B9 set_ay absORa,0
00328B 1 67 02 28
00328E 1 01 4C ora (indOR,x)
003290 1 08 D9 73 02 tst_ay absrlo,absflo,0
003294 1 D0 FE 68 49
003298 1 30 D9 77 02
00329E 1 CA dex
00329F 1 CA dex
0032A0 1 88 dey
0032A1 1 10 E4 bpl tora12
0032A3 1 A2 06 ldx #6
0032A5 1 A0 03 ldy #3
0032A7 1 tora13:
0032A7 1 A9 FF 48 B9 set_ay absORa,$ff
0032AB 1 67 02 28
0032AE 1 01 4C ora (indOR,x)
0032B0 1 08 D9 73 02 tst_ay absrlo,absflo,$ff-fnz
0032B4 1 D0 FE 68 49
0032B8 1 7D D9 77 02
0032BE 1 CA dex
0032BF 1 CA dex
0032C0 1 88 dey
0032C1 1 10 E4 bpl tora13
0032C3 1
0032C3 1 A0 03 ldy #3 ;(zp),y
0032C5 1 tora14:
0032C5 1 A9 00 48 B9 set_ay absORa,0
0032C9 1 67 02 28
0032CC 1 11 4C ora (indOR),y
0032CE 1 08 D9 73 02 tst_ay absrlo,absflo,0
0032D2 1 D0 FE 68 49
0032D6 1 30 D9 77 02
0032DC 1 88 dey
0032DD 1 10 E6 bpl tora14
0032DF 1 A0 03 ldy #3
0032E1 1 tora15:
0032E1 1 A9 FF 48 B9 set_ay absORa,$ff
0032E5 1 67 02 28
0032E8 1 11 4C ora (indOR),y
0032EA 1 08 D9 73 02 tst_ay absrlo,absflo,$ff-fnz
0032EE 1 D0 FE 68 49
0032F2 1 7D D9 77 02
0032F8 1 88 dey
0032F9 1 10 E6 bpl tora15
0032FB 1 .if I_flag = 3
0032FB 1 58 cli
0032FC 1 .endif
0032FC 1 AD 00 02 C9 next_test
003300 1 28 D0 FE A9
003304 1 29 8D 00 02
003308 1
003308 1 ; full binary add/subtract test
003308 1 ; iterates through all combinations of operands and carry input
003308 1 ; uses increments/decrements to predict result & result flags
003308 1 D8 cld
003309 1 A2 0E ldx #ad2 ;for indexed test
00330B 1 A0 FF ldy #$ff ;max range
00330D 1 A9 00 lda #0 ;start with adding zeroes & no carry
00330F 1 85 0C sta adfc ;carry in - for diag
003311 1 85 0D sta ad1 ;operand 1 - accumulator
003313 1 85 0E sta ad2 ;operand 2 - memory or immediate
003315 1 8D 03 02 sta ada2 ;non zp
003318 1 85 0F sta adrl ;expected result bits 0-7
00331A 1 85 10 sta adrh ;expected result bit 8 (carry out)
00331C 1 A9 FF lda #$ff ;complemented operand 2 for subtract
00331E 1 85 12 sta sb2
003320 1 8D 04 02 sta sba2 ;non zp
003323 1 A9 02 lda #2 ;expected Z-flag
003325 1 85 11 sta adrf
003327 1 18 tadd: clc ;test with carry clear
003328 1 20 A2 35 jsr chkadd
00332B 1 E6 0C inc adfc ;now with carry
00332D 1 E6 0F inc adrl ;result +1
00332F 1 08 php ;save N & Z from low result
003330 1 08 php
003331 1 68 pla ;accu holds expected flags
003332 1 29 82 and #$82 ;mask N & Z
003334 1 28 plp
003335 1 D0 02 bne tadd1
003337 1 E6 10 inc adrh ;result bit 8 - carry
003339 1 05 10 tadd1: ora adrh ;merge C to expected flags
00333B 1 85 11 sta adrf ;save expected flags except overflow
00333D 1 38 sec ;test with carry set
00333E 1 20 A2 35 jsr chkadd
003341 1 C6 0C dec adfc ;same for operand +1 but no carry
003343 1 E6 0D inc ad1
003345 1 D0 E0 bne tadd ;iterate op1
003347 1 A9 00 lda #0 ;preset result to op2 when op1 = 0
003349 1 85 10 sta adrh
00334B 1 EE 03 02 inc ada2
00334E 1 E6 0E inc ad2
003350 1 08 php ;save NZ as operand 2 becomes the new result
003351 1 68 pla
003352 1 29 82 and #$82 ;mask N00000Z0
003354 1 85 11 sta adrf ;no need to check carry as we are adding to 0
003356 1 C6 12 dec sb2 ;complement subtract operand 2
003358 1 CE 04 02 dec sba2
00335B 1 A5 0E lda ad2
00335D 1 85 0F sta adrl
00335F 1 D0 C6 bne tadd ;iterate op2
003361 1 .if disable_decimal < 1
003361 1 AD 00 02 C9 next_test
003365 1 29 D0 FE A9
003369 1 2A 8D 00 02
00336D 1
00336D 1 ; decimal add/subtract test
00336D 1 ; *** WARNING - tests documented behavior only! ***
00336D 1 ; only valid BCD operands are tested, N V Z flags are ignored
00336D 1 ; iterates through all valid combinations of operands and carry input
00336D 1 ; uses increments/decrements to predict result & carry flag
00336D 1 F8 sed
00336E 1 A2 0E ldx #ad2 ;for indexed test
003370 1 A0 FF ldy #$ff ;max range
003372 1 A9 99 lda #$99 ;start with adding 99 to 99 with carry
003374 1 85 0D sta ad1 ;operand 1 - accumulator
003376 1 85 0E sta ad2 ;operand 2 - memory or immediate
003378 1 8D 03 02 sta ada2 ;non zp
00337B 1 85 0F sta adrl ;expected result bits 0-7
00337D 1 A9 01 lda #1 ;set carry in & out
00337F 1 85 0C sta adfc ;carry in - for diag
003381 1 85 10 sta adrh ;expected result bit 8 (carry out)
003383 1 A9 00 lda #0 ;complemented operand 2 for subtract
003385 1 85 12 sta sb2
003387 1 8D 04 02 sta sba2 ;non zp
00338A 1 38 tdad: sec ;test with carry set
00338B 1 20 6F 34 jsr chkdad
00338E 1 C6 0C dec adfc ;now with carry clear
003390 1 A5 0F lda adrl ;decimal adjust result
003392 1 D0 08 bne tdad1 ;skip clear carry & preset result 99 (9A-1)
003394 1 C6 10 dec adrh
003396 1 A9 99 lda #$99
003398 1 85 0F sta adrl
00339A 1 D0 12 bne tdad3
00339C 1 29 0F tdad1: and #$f ;lower nibble mask
00339E 1 D0 0C bne tdad2 ;no decimal adjust needed
0033A0 1 C6 0F dec adrl ;decimal adjust (?0-6)
0033A2 1 C6 0F dec adrl
0033A4 1 C6 0F dec adrl
0033A6 1 C6 0F dec adrl
0033A8 1 C6 0F dec adrl
0033AA 1 C6 0F dec adrl
0033AC 1 C6 0F tdad2: dec adrl ;result -1
0033AE 1 18 tdad3: clc ;test with carry clear
0033AF 1 20 6F 34 jsr chkdad
0033B2 1 E6 0C inc adfc ;same for operand -1 but with carry
0033B4 1 A5 0D lda ad1 ;decimal adjust operand 1
0033B6 1 F0 15 beq tdad5 ;iterate operand 2
0033B8 1 29 0F and #$f ;lower nibble mask
0033BA 1 D0 0C bne tdad4 ;skip decimal adjust
0033BC 1 C6 0D dec ad1 ;decimal adjust (?0-6)
0033BE 1 C6 0D dec ad1
0033C0 1 C6 0D dec ad1
0033C2 1 C6 0D dec ad1
0033C4 1 C6 0D dec ad1
0033C6 1 C6 0D dec ad1
0033C8 1 C6 0D tdad4: dec ad1 ;operand 1 -1
0033CA 1 4C 8A 33 jmp tdad ;iterate op1
0033CD 1
0033CD 1 A9 99 tdad5: lda #$99 ;precharge op1 max
0033CF 1 85 0D sta ad1
0033D1 1 A5 0E lda ad2 ;decimal adjust operand 2
0033D3 1 F0 30 beq tdad7 ;end of iteration
0033D5 1 29 0F and #$f ;lower nibble mask
0033D7 1 D0 18 bne tdad6 ;skip decimal adjust
0033D9 1 C6 0E dec ad2 ;decimal adjust (?0-6)
0033DB 1 C6 0E dec ad2
0033DD 1 C6 0E dec ad2
0033DF 1 C6 0E dec ad2
0033E1 1 C6 0E dec ad2
0033E3 1 C6 0E dec ad2
0033E5 1 E6 12 inc sb2 ;complemented decimal adjust for subtract (?9+6)
0033E7 1 E6 12 inc sb2
0033E9 1 E6 12 inc sb2
0033EB 1 E6 12 inc sb2
0033ED 1 E6 12 inc sb2
0033EF 1 E6 12 inc sb2
0033F1 1 C6 0E tdad6: dec ad2 ;operand 2 -1
0033F3 1 E6 12 inc sb2 ;complemented operand for subtract
0033F5 1 A5 12 lda sb2
0033F7 1 8D 04 02 sta sba2 ;copy as non zp operand
0033FA 1 A5 0E lda ad2
0033FC 1 8D 03 02 sta ada2 ;copy as non zp operand
0033FF 1 85 0F sta adrl ;new result since op1+carry=00+carry +op2=op2
003401 1 E6 10 inc adrh ;result carry
003403 1 D0 85 bne tdad ;iterate op2
003405 1 tdad7:
003405 1 AD 00 02 C9 next_test
003409 1 2A D0 FE A9
00340D 1 2B 8D 00 02
003411 1
003411 1 ; decimal/binary switch test
003411 1 ; tests CLD, SED, PLP, RTI to properly switch between decimal & binary opcode
003411 1 ; tables
003411 1 18 clc
003412 1 D8 cld
003413 1 08 php
003414 1 A9 55 lda #$55
003416 1 69 55 adc #$55
003418 1 C9 AA cmp #$aa
00341A 1 D0 FE trap_ne ;expected binary result after cld
00341C 1 18 clc
00341D 1 F8 sed
00341E 1 08 php
00341F 1 A9 55 lda #$55
003421 1 69 55 adc #$55
003423 1 C9 10 cmp #$10
003425 1 D0 FE trap_ne ;expected decimal result after sed
003427 1 D8 cld
003428 1 28 plp
003429 1 A9 55 lda #$55
00342B 1 69 55 adc #$55
00342D 1 C9 10 cmp #$10
00342F 1 D0 FE trap_ne ;expected decimal result after plp D=1
003431 1 28 plp
003432 1 A9 55 lda #$55
003434 1 69 55 adc #$55
003436 1 C9 AA cmp #$aa
003438 1 D0 FE trap_ne ;expected binary result after plp D=0
00343A 1 18 clc
00343B 1 A9 34 lda #>bin_rti_ret ;emulated interrupt for rti
00343D 1 48 pha
00343E 1 A9 55 lda #<bin_rti_ret
003440 1 48 pha
003441 1 08 php
003442 1 F8 sed
003443 1 A9 34 lda #>dec_rti_ret ;emulated interrupt for rti
003445 1 48 pha
003446 1 A9 4C lda #<dec_rti_ret
003448 1 48 pha
003449 1 08 php
00344A 1 D8 cld
00344B 1 40 rti
00344C 1 dec_rti_ret:
00344C 1 A9 55 lda #$55
00344E 1 69 55 adc #$55
003450 1 C9 10 cmp #$10
003452 1 D0 FE trap_ne ;expected decimal result after rti D=1
003454 1 40 rti
003455 1 bin_rti_ret:
003455 1 A9 55 lda #$55
003457 1 69 55 adc #$55
003459 1 C9 AA cmp #$aa
00345B 1 D0 FE trap_ne ;expected binary result after rti D=0
00345D 1 .endif
00345D 1
00345D 1 AD 00 02 lda test_case
003460 1 C9 2B cmp #test_num
003462 1 D0 FE trap_ne ;previous test is out of sequence
003464 1 A9 F0 lda #$f0 ;mark opcode testing complete
003466 1 8D 00 02 sta test_case
003469 1
003469 1 ; final RAM integrity test
003469 1 ; verifies that none of the previous tests has altered RAM outside of the
003469 1 ; designated write areas.
003469 1 check_ram
003469 1 ; *** DEBUG INFO ***
003469 1 ; to debug checksum errors uncomment check_ram in the next_test macro to
003469 1 ; narrow down the responsible opcode.
003469 1 ; may give false errors when monitor, OS or other background activity is
003469 1 ; allowed during previous tests.
003469 1
003469 1
003469 1 ; S U C C E S S ************************************************
003469 1 ; -------------
003469 1 4C 69 34 success ;if you get here everything went well
00346C 1 ; -------------
00346C 1 ; S U C C E S S ************************************************
00346C 1 4C 00 04 jmp start ;run again
00346F 1
00346F 1 .if disable_decimal < 1
00346F 1 ; core subroutine of the decimal add/subtract test
00346F 1 ; *** WARNING - tests documented behavior only! ***
00346F 1 ; only valid BCD operands are tested, N V Z flags are ignored
00346F 1 ; iterates through all valid combinations of operands and carry input
00346F 1 ; uses increments/decrements to predict result & carry flag
00346F 1 chkdad:
00346F 1 ; decimal ADC / SBC zp
00346F 1 08 php ;save carry for subtract
003470 1 A5 0D lda ad1
003472 1 65 0E adc ad2 ;perform add
003474 1 08 php
003475 1 C5 0F cmp adrl ;check result
003477 1 D0 FE trap_ne ;bad result
003479 1 68 pla ;check flags
00347A 1 29 01 and #1 ;mask carry
00347C 1 C5 10 cmp adrh
00347E 1 D0 FE trap_ne ;bad carry
003480 1 28 plp
003481 1 08 php ;save carry for next add
003482 1 A5 0D lda ad1
003484 1 E5 12 sbc sb2 ;perform subtract
003486 1 08 php
003487 1 C5 0F cmp adrl ;check result
003489 1 D0 FE trap_ne ;bad result
00348B 1 68 pla ;check flags
00348C 1 29 01 and #1 ;mask carry
00348E 1 C5 10 cmp adrh
003490 1 D0 FE trap_ne ;bad flags
003492 1 28 plp
003493 1 ; decimal ADC / SBC abs
003493 1 08 php ;save carry for subtract
003494 1 A5 0D lda ad1
003496 1 6D 03 02 adc ada2 ;perform add
003499 1 08 php
00349A 1 C5 0F cmp adrl ;check result
00349C 1 D0 FE trap_ne ;bad result
00349E 1 68 pla ;check flags
00349F 1 29 01 and #1 ;mask carry
0034A1 1 C5 10 cmp adrh
0034A3 1 D0 FE trap_ne ;bad carry
0034A5 1 28 plp
0034A6 1 08 php ;save carry for next add
0034A7 1 A5 0D lda ad1
0034A9 1 ED 04 02 sbc sba2 ;perform subtract
0034AC 1 08 php
0034AD 1 C5 0F cmp adrl ;check result
0034AF 1 D0 FE trap_ne ;bad result
0034B1 1 68 pla ;check flags
0034B2 1 29 01 and #1 ;mask carry
0034B4 1 C5 10 cmp adrh
0034B6 1 D0 FE trap_ne ;bad carry
0034B8 1 28 plp
0034B9 1 ; decimal ADC / SBC #
0034B9 1 08 php ;save carry for subtract
0034BA 1 A5 0E lda ad2
0034BC 1 8D 13 02 sta ex_adci+1 ;set ADC # operand
0034BF 1 A5 0D lda ad1
0034C1 1 20 12 02 jsr ex_adci ;execute ADC # in RAM
0034C4 1 08 php
0034C5 1 C5 0F cmp adrl ;check result
0034C7 1 D0 FE trap_ne ;bad result
0034C9 1 68 pla ;check flags
0034CA 1 29 01 and #1 ;mask carry
0034CC 1 C5 10 cmp adrh
0034CE 1 D0 FE trap_ne ;bad carry
0034D0 1 28 plp
0034D1 1 08 php ;save carry for next add
0034D2 1 A5 12 lda sb2
0034D4 1 8D 16 02 sta ex_sbci+1 ;set SBC # operand
0034D7 1 A5 0D lda ad1
0034D9 1 20 15 02 jsr ex_sbci ;execute SBC # in RAM
0034DC 1 08 php
0034DD 1 C5 0F cmp adrl ;check result
0034DF 1 D0 FE trap_ne ;bad result
0034E1 1 68 pla ;check flags
0034E2 1 29 01 and #1 ;mask carry
0034E4 1 C5 10 cmp adrh
0034E6 1 D0 FE trap_ne ;bad carry
0034E8 1 28 plp
0034E9 1 ; decimal ADC / SBC zp,x
0034E9 1 08 php ;save carry for subtract
0034EA 1 A5 0D lda ad1
0034EC 1 75 00 adc 0,x ;perform add
0034EE 1 08 php
0034EF 1 C5 0F cmp adrl ;check result
0034F1 1 D0 FE trap_ne ;bad result
0034F3 1 68 pla ;check flags
0034F4 1 29 01 and #1 ;mask carry
0034F6 1 C5 10 cmp adrh
0034F8 1 D0 FE trap_ne ;bad carry
0034FA 1 28 plp
0034FB 1 08 php ;save carry for next add
0034FC 1 A5 0D lda ad1
0034FE 1 F5 04 sbc sb2-ad2,x ;perform subtract
003500 1 08 php
003501 1 C5 0F cmp adrl ;check result
003503 1 D0 FE trap_ne ;bad result
003505 1 68 pla ;check flags
003506 1 29 01 and #1 ;mask carry
003508 1 C5 10 cmp adrh
00350A 1 D0 FE trap_ne ;bad carry
00350C 1 28 plp
00350D 1 ; decimal ADC / SBC abs,x
00350D 1 08 php ;save carry for subtract
00350E 1 A5 0D lda ad1
003510 1 7D F5 01 adc ada2-ad2,x ;perform add
003513 1 08 php
003514 1 C5 0F cmp adrl ;check result
003516 1 D0 FE trap_ne ;bad result
003518 1 68 pla ;check flags
003519 1 29 01 and #1 ;mask carry
00351B 1 C5 10 cmp adrh
00351D 1 D0 FE trap_ne ;bad carry
00351F 1 28 plp
003520 1 08 php ;save carry for next add
003521 1 A5 0D lda ad1
003523 1 FD F6 01 sbc sba2-ad2,x ;perform subtract
003526 1 08 php
003527 1 C5 0F cmp adrl ;check result
003529 1 D0 FE trap_ne ;bad result
00352B 1 68 pla ;check flags
00352C 1 29 01 and #1 ;mask carry
00352E 1 C5 10 cmp adrh
003530 1 D0 FE trap_ne ;bad carry
003532 1 28 plp
003533 1 ; decimal ADC / SBC abs,y
003533 1 08 php ;save carry for subtract
003534 1 A5 0D lda ad1
003536 1 79 04 01 adc ada2-$ff,y ;perform add
003539 1 08 php
00353A 1 C5 0F cmp adrl ;check result
00353C 1 D0 FE trap_ne ;bad result
00353E 1 68 pla ;check flags
00353F 1 29 01 and #1 ;mask carry
003541 1 C5 10 cmp adrh
003543 1 D0 FE trap_ne ;bad carry
003545 1 28 plp
003546 1 08 php ;save carry for next add
003547 1 A5 0D lda ad1
003549 1 F9 05 01 sbc sba2-$ff,y ;perform subtract
00354C 1 08 php
00354D 1 C5 0F cmp adrl ;check result
00354F 1 D0 FE trap_ne ;bad result
003551 1 68 pla ;check flags
003552 1 29 01 and #1 ;mask carry
003554 1 C5 10 cmp adrh
003556 1 D0 FE trap_ne ;bad carry
003558 1 28 plp
003559 1 ; decimal ADC / SBC (zp,x)
003559 1 08 php ;save carry for subtract
00355A 1 A5 0D lda ad1
00355C 1 61 46 adc (<adi2-ad2,x) ;perform add
00355E 1 08 php
00355F 1 C5 0F cmp adrl ;check result
003561 1 D0 FE trap_ne ;bad result
003563 1 68 pla ;check flags
003564 1 29 01 and #1 ;mask carry
003566 1 C5 10 cmp adrh
003568 1 D0 FE trap_ne ;bad carry
00356A 1 28 plp
00356B 1 08 php ;save carry for next add
00356C 1 A5 0D lda ad1
00356E 1 E1 48 sbc (<sbi2-ad2,x) ;perform subtract
003570 1 08 php
003571 1 C5 0F cmp adrl ;check result
003573 1 D0 FE trap_ne ;bad result
003575 1 68 pla ;check flags
003576 1 29 01 and #1 ;mask carry
003578 1 C5 10 cmp adrh
00357A 1 D0 FE trap_ne ;bad carry
00357C 1 28 plp
00357D 1 ; decimal ADC / SBC (abs),y
00357D 1 08 php ;save carry for subtract
00357E 1 A5 0D lda ad1
003580 1 71 58 adc (adiy2),y ;perform add
003582 1 08 php
003583 1 C5 0F cmp adrl ;check result
003585 1 D0 FE trap_ne ;bad result
003587 1 68 pla ;check flags
003588 1 29 01 and #1 ;mask carry
00358A 1 C5 10 cmp adrh
00358C 1 D0 FE trap_ne ;bad carry
00358E 1 28 plp
00358F 1 08 php ;save carry for next add
003590 1 A5 0D lda ad1
003592 1 F1 5A sbc (sbiy2),y ;perform subtract
003594 1 08 php
003595 1 C5 0F cmp adrl ;check result
003597 1 D0 FE trap_ne ;bad result
003599 1 68 pla ;check flags
00359A 1 29 01 and #1 ;mask carry
00359C 1 C5 10 cmp adrh
00359E 1 D0 FE trap_ne ;bad carry
0035A0 1 28 plp
0035A1 1 60 rts
0035A2 1 .endif
0035A2 1
0035A2 1 ; core subroutine of the full binary add/subtract test
0035A2 1 ; iterates through all combinations of operands and carry input
0035A2 1 ; uses increments/decrements to predict result & result flags
0035A2 1 A5 11 chkadd: lda adrf ;add V-flag if overflow
0035A4 1 29 83 and #$83 ;keep N-----ZC / clear V
0035A6 1 48 pha
0035A7 1 A5 0D lda ad1 ;test sign unequal between operands
0035A9 1 45 0E eor ad2
0035AB 1 30 0A bmi ckad1 ;no overflow possible - operands have different sign
0035AD 1 A5 0D lda ad1 ;test sign equal between operands and result
0035AF 1 45 0F eor adrl
0035B1 1 10 04 bpl ckad1 ;no overflow occured - operand and result have same sign
0035B3 1 68 pla
0035B4 1 09 40 ora #$40 ;set V
0035B6 1 48 pha
0035B7 1 68 ckad1: pla
0035B8 1 85 11 sta adrf ;save expected flags
0035BA 1 ; binary ADC / SBC zp
0035BA 1 08 php ;save carry for subtract
0035BB 1 A5 0D lda ad1
0035BD 1 65 0E adc ad2 ;perform add
0035BF 1 08 php
0035C0 1 C5 0F cmp adrl ;check result
0035C2 1 D0 FE trap_ne ;bad result
0035C4 1 68 pla ;check flags
0035C5 1 29 C3 and #$c3 ;mask NV----ZC
0035C7 1 C5 11 cmp adrf
0035C9 1 D0 FE trap_ne ;bad flags
0035CB 1 28 plp
0035CC 1 08 php ;save carry for next add
0035CD 1 A5 0D lda ad1
0035CF 1 E5 12 sbc sb2 ;perform subtract
0035D1 1 08 php
0035D2 1 C5 0F cmp adrl ;check result
0035D4 1 D0 FE trap_ne ;bad result
0035D6 1 68 pla ;check flags
0035D7 1 29 C3 and #$c3 ;mask NV----ZC
0035D9 1 C5 11 cmp adrf
0035DB 1 D0 FE trap_ne ;bad flags
0035DD 1 28 plp
0035DE 1 ; binary ADC / SBC abs
0035DE 1 08 php ;save carry for subtract
0035DF 1 A5 0D lda ad1
0035E1 1 6D 03 02 adc ada2 ;perform add
0035E4 1 08 php
0035E5 1 C5 0F cmp adrl ;check result
0035E7 1 D0 FE trap_ne ;bad result
0035E9 1 68 pla ;check flags
0035EA 1 29 C3 and #$c3 ;mask NV----ZC
0035EC 1 C5 11 cmp adrf
0035EE 1 D0 FE trap_ne ;bad flags
0035F0 1 28 plp
0035F1 1 08 php ;save carry for next add
0035F2 1 A5 0D lda ad1
0035F4 1 ED 04 02 sbc sba2 ;perform subtract
0035F7 1 08 php
0035F8 1 C5 0F cmp adrl ;check result
0035FA 1 D0 FE trap_ne ;bad result
0035FC 1 68 pla ;check flags
0035FD 1 29 C3 and #$c3 ;mask NV----ZC
0035FF 1 C5 11 cmp adrf
003601 1 D0 FE trap_ne ;bad flags
003603 1 28 plp
003604 1 ; binary ADC / SBC #
003604 1 08 php ;save carry for subtract
003605 1 A5 0E lda ad2
003607 1 8D 13 02 sta ex_adci+1 ;set ADC # operand
00360A 1 A5 0D lda ad1
00360C 1 20 12 02 jsr ex_adci ;execute ADC # in RAM
00360F 1 08 php
003610 1 C5 0F cmp adrl ;check result
003612 1 D0 FE trap_ne ;bad result
003614 1 68 pla ;check flags
003615 1 29 C3 and #$c3 ;mask NV----ZC
003617 1 C5 11 cmp adrf
003619 1 D0 FE trap_ne ;bad flags
00361B 1 28 plp
00361C 1 08 php ;save carry for next add
00361D 1 A5 12 lda sb2
00361F 1 8D 16 02 sta ex_sbci+1 ;set SBC # operand
003622 1 A5 0D lda ad1
003624 1 20 15 02 jsr ex_sbci ;execute SBC # in RAM
003627 1 08 php
003628 1 C5 0F cmp adrl ;check result
00362A 1 D0 FE trap_ne ;bad result
00362C 1 68 pla ;check flags
00362D 1 29 C3 and #$c3 ;mask NV----ZC
00362F 1 C5 11 cmp adrf
003631 1 D0 FE trap_ne ;bad flags
003633 1 28 plp
003634 1 ; binary ADC / SBC zp,x
003634 1 08 php ;save carry for subtract
003635 1 A5 0D lda ad1
003637 1 75 00 adc 0,x ;perform add
003639 1 08 php
00363A 1 C5 0F cmp adrl ;check result
00363C 1 D0 FE trap_ne ;bad result
00363E 1 68 pla ;check flags
00363F 1 29 C3 and #$c3 ;mask NV----ZC
003641 1 C5 11 cmp adrf
003643 1 D0 FE trap_ne ;bad flags
003645 1 28 plp
003646 1 08 php ;save carry for next add
003647 1 A5 0D lda ad1
003649 1 F5 04 sbc sb2-ad2,x ;perform subtract
00364B 1 08 php
00364C 1 C5 0F cmp adrl ;check result
00364E 1 D0 FE trap_ne ;bad result
003650 1 68 pla ;check flags
003651 1 29 C3 and #$c3 ;mask NV----ZC
003653 1 C5 11 cmp adrf
003655 1 D0 FE trap_ne ;bad flags
003657 1 28 plp
003658 1 ; binary ADC / SBC abs,x
003658 1 08 php ;save carry for subtract
003659 1 A5 0D lda ad1
00365B 1 7D F5 01 adc ada2-ad2,x ;perform add
00365E 1 08 php
00365F 1 C5 0F cmp adrl ;check result
003661 1 D0 FE trap_ne ;bad result
003663 1 68 pla ;check flags
003664 1 29 C3 and #$c3 ;mask NV----ZC
003666 1 C5 11 cmp adrf
003668 1 D0 FE trap_ne ;bad flags
00366A 1 28 plp
00366B 1 08 php ;save carry for next add
00366C 1 A5 0D lda ad1
00366E 1 FD F6 01 sbc sba2-ad2,x ;perform subtract
003671 1 08 php
003672 1 C5 0F cmp adrl ;check result
003674 1 D0 FE trap_ne ;bad result
003676 1 68 pla ;check flags
003677 1 29 C3 and #$c3 ;mask NV----ZC
003679 1 C5 11 cmp adrf
00367B 1 D0 FE trap_ne ;bad flags
00367D 1 28 plp
00367E 1 ; binary ADC / SBC abs,y
00367E 1 08 php ;save carry for subtract
00367F 1 A5 0D lda ad1
003681 1 79 04 01 adc ada2-$ff,y ;perform add
003684 1 08 php
003685 1 C5 0F cmp adrl ;check result
003687 1 D0 FE trap_ne ;bad result
003689 1 68 pla ;check flags
00368A 1 29 C3 and #$c3 ;mask NV----ZC
00368C 1 C5 11 cmp adrf
00368E 1 D0 FE trap_ne ;bad flags
003690 1 28 plp
003691 1 08 php ;save carry for next add
003692 1 A5 0D lda ad1
003694 1 F9 05 01 sbc sba2-$ff,y ;perform subtract
003697 1 08 php
003698 1 C5 0F cmp adrl ;check result
00369A 1 D0 FE trap_ne ;bad result
00369C 1 68 pla ;check flags
00369D 1 29 C3 and #$c3 ;mask NV----ZC
00369F 1 C5 11 cmp adrf
0036A1 1 D0 FE trap_ne ;bad flags
0036A3 1 28 plp
0036A4 1 ; binary ADC / SBC (zp,x)
0036A4 1 08 php ;save carry for subtract
0036A5 1 A5 0D lda ad1
0036A7 1 61 46 adc (<adi2-ad2,x) ;perform add
0036A9 1 08 php
0036AA 1 C5 0F cmp adrl ;check result
0036AC 1 D0 FE trap_ne ;bad result
0036AE 1 68 pla ;check flags
0036AF 1 29 C3 and #$c3 ;mask NV----ZC
0036B1 1 C5 11 cmp adrf
0036B3 1 D0 FE trap_ne ;bad flags
0036B5 1 28 plp
0036B6 1 08 php ;save carry for next add
0036B7 1 A5 0D lda ad1
0036B9 1 E1 48 sbc (<sbi2-ad2,x) ;perform subtract
0036BB 1 08 php
0036BC 1 C5 0F cmp adrl ;check result
0036BE 1 D0 FE trap_ne ;bad result
0036C0 1 68 pla ;check flags
0036C1 1 29 C3 and #$c3 ;mask NV----ZC
0036C3 1 C5 11 cmp adrf
0036C5 1 D0 FE trap_ne ;bad flags
0036C7 1 28 plp
0036C8 1 ; binary ADC / SBC (abs),y
0036C8 1 08 php ;save carry for subtract
0036C9 1 A5 0D lda ad1
0036CB 1 71 58 adc (adiy2),y ;perform add
0036CD 1 08 php
0036CE 1 C5 0F cmp adrl ;check result
0036D0 1 D0 FE trap_ne ;bad result
0036D2 1 68 pla ;check flags
0036D3 1 29 C3 and #$c3 ;mask NV----ZC
0036D5 1 C5 11 cmp adrf
0036D7 1 D0 FE trap_ne ;bad flags
0036D9 1 28 plp
0036DA 1 08 php ;save carry for next add
0036DB 1 A5 0D lda ad1
0036DD 1 F1 5A sbc (sbiy2),y ;perform subtract
0036DF 1 08 php
0036E0 1 C5 0F cmp adrl ;check result
0036E2 1 D0 FE trap_ne ;bad result
0036E4 1 68 pla ;check flags
0036E5 1 29 C3 and #$c3 ;mask NV----ZC
0036E7 1 C5 11 cmp adrf
0036E9 1 D0 FE trap_ne ;bad flags
0036EB 1 28 plp
0036EC 1 60 rts
0036ED 1
0036ED 1 ; target for the jump absolute test
0036ED 1 88 dey
0036EE 1 88 dey
0036EF 1 test_far:
0036EF 1 08 php ;either SP or Y count will fail, if we do not hit
0036F0 1 88 dey
0036F1 1 88 dey
0036F2 1 88 dey
0036F3 1 28 plp
0036F4 1 B0 FE trap_cs ;flags loaded?
0036F6 1 70 FE trap_vs
0036F8 1 30 FE trap_mi
0036FA 1 F0 FE trap_eq
0036FC 1 C9 46 cmp #'F' ;registers loaded?
0036FE 1 D0 FE trap_ne
003700 1 E0 41 cpx #'A'
003702 1 D0 FE trap_ne
003704 1 C0 4F cpy #('R'-3)
003706 1 D0 FE trap_ne
003708 1 48 pha ;save a,x
003709 1 8A txa
00370A 1 48 pha
00370B 1 BA tsx
00370C 1 E0 FD cpx #$fd ;check SP
00370E 1 D0 FE trap_ne
003710 1 68 pla ;restore x
003711 1 AA tax
003712 1 A9 FF 48 28 set_stat $ff
003716 1 68 pla ;restore a
003717 1 E8 inx ;return registers with modifications
003718 1 49 AA eor #$aa ;N=1, V=1, Z=0, C=1
00371A 1 4C 0F 09 jmp far_ret
00371D 1
00371D 1 ; target for the jump indirect test
00371D 1 ; .align 2
00371D 1 .if * & 1 ; workaround for problems with .align 2
00371D 1 00 .byte 0 ;
00371E 1 .endif ;
00371E 1 ptr_tst_ind:
00371E 1 27 37 .word test_ind
003720 1 ptr_ind_ret:
003720 1 64 09 .word ind_ret
003722 1 4C 22 37 trap ;runover protection
003725 1 88 dey
003726 1 88 dey
003727 1 test_ind:
003727 1 08 php ;either SP or Y count will fail, if we do not hit
003728 1 88 dey
003729 1 88 dey
00372A 1 88 dey
00372B 1 28 plp
00372C 1 B0 FE trap_cs ;flags loaded?
00372E 1 70 FE trap_vs
003730 1 30 FE trap_mi
003732 1 F0 FE trap_eq
003734 1 C9 49 cmp #'I' ;registers loaded?
003736 1 D0 FE trap_ne
003738 1 E0 4E cpx #'N'
00373A 1 D0 FE trap_ne
00373C 1 C0 41 cpy #('D'-3)
00373E 1 D0 FE trap_ne
003740 1 48 pha ;save a,x
003741 1 8A txa
003742 1 48 pha
003743 1 BA tsx
003744 1 E0 FD cpx #$fd ;check SP
003746 1 D0 FE trap_ne
003748 1 68 pla ;restore x
003749 1 AA tax
00374A 1 A9 FF 48 28 set_stat $ff
00374E 1 68 pla ;restore a
00374F 1 E8 inx ;return registers with modifications
003750 1 49 AA eor #$aa ;N=1, V=1, Z=0, C=1
003752 1 6C 20 37 jmp (ptr_ind_ret)
003755 1 4C 55 37 trap ;runover protection
003758 1 4C 00 04 jmp start ;catastrophic error - cannot continue
00375B 1
00375B 1 ; target for the jump subroutine test
00375B 1 88 dey
00375C 1 88 dey
00375D 1 test_jsr:
00375D 1 08 php ;either SP or Y count will fail, if we do not hit
00375E 1 88 dey
00375F 1 88 dey
003760 1 88 dey
003761 1 28 plp
003762 1 B0 FE trap_cs ;flags loaded?
003764 1 70 FE trap_vs
003766 1 30 FE trap_mi
003768 1 F0 FE trap_eq
00376A 1 C9 4A cmp #'J' ;registers loaded?
00376C 1 D0 FE trap_ne
00376E 1 E0 53 cpx #'S'
003770 1 D0 FE trap_ne
003772 1 C0 4F cpy #('R'-3)
003774 1 D0 FE trap_ne
003776 1 48 pha ;save a,x
003777 1 8A txa
003778 1 48 pha
003779 1 BA tsx ;sp -4? (return addr,a,x)
00377A 1 E0 FB cpx #$fb
00377C 1 D0 FE trap_ne
00377E 1 AD FF 01 lda $1ff ;propper return on stack
003781 1 C9 09 cmp #>jsr_ret
003783 1 D0 FE trap_ne
003785 1 AD FE 01 lda $1fe
003788 1 C9 9A cmp #<jsr_ret
00378A 1 D0 FE trap_ne
00378C 1 A9 FF 48 28 set_stat $ff
003790 1 68 pla ;pull x,a
003791 1 AA tax
003792 1 68 pla
003793 1 E8 inx ;return registers with modifications
003794 1 49 AA eor #$aa ;N=1, V=1, Z=0, C=1
003796 1 60 rts
003797 1 4C 97 37 trap ;runover protection
00379A 1 4C 00 04 jmp start ;catastrophic error - cannot continue
00379D 1
00379D 1 ;trap in case of unexpected IRQ, NMI, BRK, RESET - BRK test target
00379D 1 nmi_trap:
00379D 1 4C 9D 37 trap ;check stack for conditions at NMI
0037A0 1 4C 00 04 jmp start ;catastrophic error - cannot continue
0037A3 1 res_trap:
0037A3 1 4C A3 37 trap ;unexpected RESET
0037A6 1 4C 00 04 jmp start ;catastrophic error - cannot continue
0037A9 1
0037A9 1 88 dey
0037AA 1 88 dey
0037AB 1 irq_trap: ;BRK test or unextpected BRK or IRQ
0037AB 1 08 php ;either SP or Y count will fail, if we do not hit
0037AC 1 88 dey
0037AD 1 88 dey
0037AE 1 88 dey
0037AF 1 ;next traps could be caused by unexpected BRK or IRQ
0037AF 1 ;check stack for BREAK and originating location
0037AF 1 ;possible jump/branch into weeds (uninitialized space)
0037AF 1 C9 BD cmp #$ff-'B' ;BRK pass 2 registers loaded?
0037B1 1 F0 42 beq break2
0037B3 1 C9 42 cmp #'B' ;BRK pass 1 registers loaded?
0037B5 1 D0 FE trap_ne
0037B7 1 E0 52 cpx #'R'
0037B9 1 D0 FE trap_ne
0037BB 1 C0 48 cpy #'K'-3
0037BD 1 D0 FE trap_ne
0037BF 1 85 0A sta irq_a ;save registers during break test
0037C1 1 86 0B stx irq_x
0037C3 1 BA tsx ;test break on stack
0037C4 1 BD 02 01 lda $102,x
0037C7 1 C9 30 cmp_flag 0 ;break test should have B=1 & unused=1 on stack
0037C9 1 D0 FE trap_ne ; - no break flag on stack
0037CB 1 68 pla
0037CC 1 C9 34 cmp_flag intdis ;should have added interrupt disable
0037CE 1 D0 FE trap_ne
0037D0 1 BA tsx
0037D1 1 E0 FC cpx #$fc ;sp -3? (return addr, flags)
0037D3 1 D0 FE trap_ne
0037D5 1 AD FF 01 lda $1ff ;propper return on stack
0037D8 1 C9 09 cmp #>brk_ret0
0037DA 1 D0 FE trap_ne
0037DC 1 AD FE 01 lda $1fe
0037DF 1 C9 D1 cmp #<brk_ret0
0037E1 1 D0 FE trap_ne
0037E3 1 A9 FF load_flag $ff
0037E5 1 48 pha
0037E6 1 A6 0B ldx irq_x
0037E8 1 E8 inx ;return registers with modifications
0037E9 1 A5 0A lda irq_a
0037EB 1 49 AA eor #$aa
0037ED 1 28 plp ;N=1, V=1, Z=1, C=1 but original flags should be restored
0037EE 1 40 rti
0037EF 1 4C EF 37 trap ;runover protection
0037F2 1 4C 00 04 jmp start ;catastrophic error - cannot continue
0037F5 1
0037F5 1 break2: ;BRK pass 2
0037F5 1 E0 AD cpx #$ff-'R'
0037F7 1 D0 FE trap_ne
0037F9 1 C0 B1 cpy #$ff-'K'-3
0037FB 1 D0 FE trap_ne
0037FD 1 85 0A sta irq_a ;save registers during break test
0037FF 1 86 0B stx irq_x
003801 1 BA tsx ;test break on stack
003802 1 BD 02 01 lda $102,x
003805 1 C9 FF cmp_flag $ff ;break test should have B=1
003807 1 D0 FE trap_ne ; - no break flag on stack
003809 1 68 pla
00380A 1 09 08 ora #decmode ;ignore decmode cleared if 65c02
00380C 1 C9 FF cmp_flag $ff ;actual passed flags
00380E 1 D0 FE trap_ne
003810 1 BA tsx
003811 1 E0 FC cpx #$fc ;sp -3? (return addr, flags)
003813 1 D0 FE trap_ne
003815 1 AD FF 01 lda $1ff ;propper return on stack
003818 1 C9 09 cmp #>brk_ret1
00381A 1 D0 FE trap_ne
00381C 1 AD FE 01 lda $1fe
00381F 1 C9 F7 cmp #<brk_ret1
003821 1 D0 FE trap_ne
003823 1 A9 04 load_flag intdis
003825 1 48 pha
003826 1 A6 0B ldx irq_x
003828 1 E8 inx ;return registers with modifications
003829 1 A5 0A lda irq_a
00382B 1 49 AA eor #$aa
00382D 1 28 plp ;N=0, V=0, Z=0, C=0 but original flags should be restored
00382E 1 40 rti
00382F 1 4C 2F 38 trap ;runover protection
003832 1 4C 00 04 jmp start ;catastrophic error - cannot continue
003835 1
003835 1 .if report = 1
003835 1 include "report.i65"
003835 1 .endif
003835 1
003835 1 ;copy of data to initialize BSS segment
003835 1 .if load_data_direct <> 1
003835 1 zp_init:
003835 1 zps_: .byte $80,1 ;additional shift pattern to test zero result & flag
003835 1 zp1_: .byte $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
003835 1 zp7f_: .byte $7f ;test pattern for compare
003835 1 ;logical zeropage operands
003835 1 zpOR_: .byte 0,$1f,$71,$80 ;test pattern for OR
003835 1 zpAN_: .byte $0f,$ff,$7f,$80 ;test pattern for AND
003835 1 zpEO_: .byte $ff,$0f,$8f,$8f ;test pattern for EOR
003835 1 ;indirect addressing pointers
003835 1 ind1_: .word abs1 ;indirect pointer to pattern in absolute memory
003835 1 .word abs1+1
003835 1 .word abs1+2
003835 1 .word abs1+3
003835 1 .word abs7f
003835 1 inw1_: .word abs1-$f8 ;indirect pointer for wrap-test pattern
003835 1 indt_: .word abst ;indirect pointer to store area in absolute memory
003835 1 .word abst+1
003835 1 .word abst+2
003835 1 .word abst+3
003835 1 inwt_: .word abst-$f8 ;indirect pointer for wrap-test store
003835 1 indAN_: .word absAN ;indirect pointer to AND pattern in absolute memory
003835 1 .word absAN+1
003835 1 .word absAN+2
003835 1 .word absAN+3
003835 1 indEO_: .word absEO ;indirect pointer to EOR pattern in absolute memory
003835 1 .word absEO+1
003835 1 .word absEO+2
003835 1 .word absEO+3
003835 1 indOR_: .word absOR ;indirect pointer to OR pattern in absolute memory
003835 1 .word absOR+1
003835 1 .word absOR+2
003835 1 .word absOR+3
003835 1 ;add/subtract indirect pointers
003835 1 adi2_: .word ada2 ;indirect pointer to operand 2 in absolute memory
003835 1 sbi2_: .word sba2 ;indirect pointer to complemented operand 2 (SBC)
003835 1 adiy2_: .word ada2-$ff ;with offset for indirect indexed
003835 1 sbiy2_: .word sba2-$ff
003835 1 zp_end:
003835 1 .if (zp_end - zp_init) <> (zp_bss_end - zp_bss)
003835 1 ;force assembler error if size is different
003835 1 .error "mismatch between bss and zeropage data"
003835 1 .endif
003835 1 data_init:
003835 1 ex_and_:and #0 ;execute immediate opcodes
003835 1 rts
003835 1 ex_eor_:eor #0 ;execute immediate opcodes
003835 1 rts
003835 1 ex_ora_:ora #0 ;execute immediate opcodes
003835 1 rts
003835 1 ex_adc_:adc #0 ;execute immediate opcodes
003835 1 rts
003835 1 ex_sbc_:sbc #0 ;execute immediate opcodes
003835 1 rts
003835 1 ;zps: .byte $80,1 ;additional shift patterns test zero result & flag
003835 1 abs1_: .byte $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
003835 1 abs7f_: .byte $7f ;test pattern for compare
003835 1 ;loads
003835 1 fLDx_: .byte fn,fn,0,fz ;expected flags for load
003835 1 ;shifts
003835 1 rASL_: ;expected result ASL & ROL -carry
003835 1 rROL_: .byte 0,2,$86,$04,$82,0
003835 1 rROLc_: .byte 1,3,$87,$05,$83,1 ;expected result ROL +carry
003835 1 rLSR_: ;expected result LSR & ROR -carry
003835 1 rROR_: .byte $40,0,$61,$41,$20,0
003835 1 rRORc_: .byte $c0,$80,$e1,$c1,$a0,$80 ;expected result ROR +carry
003835 1 fASL_: ;expected flags for shifts
003835 1 fROL_: .byte fzc,0,fnc,fc,fn,fz ;no carry in
003835 1 fROLc_: .byte fc,0,fnc,fc,fn,0 ;carry in
003835 1 fLSR_:
003835 1 fROR_: .byte 0,fzc,fc,0,fc,fz ;no carry in
003835 1 fRORc_: .byte fn,fnc,fnc,fn,fnc,fn ;carry in
003835 1 ;increments (decrements)
003835 1 rINC_: .byte $7f,$80,$ff,0,1 ;expected result for INC/DEC
003835 1 fINC_: .byte 0,fn,fn,fz,0 ;expected flags for INC/DEC
003835 1 ;logical memory operand
003835 1 absOR_: .byte 0,$1f,$71,$80 ;test pattern for OR
003835 1 absAN_: .byte $0f,$ff,$7f,$80 ;test pattern for AND
003835 1 absEO_: .byte $ff,$0f,$8f,$8f ;test pattern for EOR
003835 1 ;logical accu operand
003835 1 absORa_:.byte 0,$f1,$1f,0 ;test pattern for OR
003835 1 absANa_:.byte $f0,$ff,$ff,$ff ;test pattern for AND
003835 1 absEOa_:.byte $ff,$f0,$f0,$0f ;test pattern for EOR
003835 1 ;logical results
003835 1 absrlo_:.byte 0,$ff,$7f,$80
003835 1 absflo_:.byte fz,fn,0,fn
003835 1 data_end
003835 1 .if (data_end - data_init) <> (data_bss_end - data_bss)
003835 1 ;force assembler error if size is different
003835 1 .error "mismatch between bss and data"
003835 1 .endif
003835 1
003835 1 vec_init
003835 1 .word nmi_trap
003835 1 .word res_trap
003835 1 .word irq_trap
003835 1 vec_bss equ $fffa
003835 1 .endif ;end of RAM init data
003835 1
003835 1 .if (load_data_direct = 1) & (ROM_vectors = 1)
003835 1 .segment "VECTORS"
003835 1 .org $fffa ;vectors
00FFFA 1 9D 37 .word nmi_trap
00FFFC 1 A3 37 .word res_trap
00FFFE 1 AB 37 .word irq_trap
010000 1 .endif
010000 1
Reference in a new issue View git blame Copy permalink