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hardware/liverpool: Explicitly state accessed registers
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21
src/orbital/hardware/liverpool/amd_regs.h
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21
src/orbital/hardware/liverpool/amd_regs.h
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@ -0,0 +1,21 @@
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/**
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* AMD utility macros for registers.
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*
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* Copyright 2017-2021. Orbital project.
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* Released under MIT license. Read LICENSE for more details.
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*
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* Authors:
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* - Alexandro Sanchez Bach <alexandro@phi.nz>
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*/
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#pragma once
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#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
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#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
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#define REG_SET_FIELD(orig_val, reg, field, field_val) \
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(((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
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(REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
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#define REG_GET_FIELD(value, reg, field) \
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(((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
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17
src/orbital/hardware/liverpool/bif/bif_regs.h
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src/orbital/hardware/liverpool/bif/bif_regs.h
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@ -0,0 +1,17 @@
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/**
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* AMD Bus Interface (BIF) device.
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*
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* Copyright 2017-2021. Orbital project.
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* Released under MIT license. Read LICENSE for more details.
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*
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* Authors:
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* - Alexandro Sanchez Bach <alexandro@phi.nz>
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*/
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#pragma once
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#include "bif/bif_4_1_d.h"
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#include "bif/bif_4_1_sh_mask.h"
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// Undocumented registers
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#define mmCC_BIF_SECURE_CNTL 0x14E3
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@ -9,11 +9,11 @@
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*/
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#include "liverpool_gc.h"
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#include "amd_regs.h"
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// Registers
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#include "acp/acp.h"
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#include "bif/bif_4_1_d.h"
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#include "bif/bif_4_1_sh_mask.h"
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#include "bif/bif_regs.h"
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#include "dce/dce_8_0_d.h"
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#include "dce/dce_8_0_sh_mask.h"
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#include "gca/gfx_7_2_d.h"
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@ -139,14 +139,14 @@ U64 LiverpoolGCDevice::mmio_read(U64 addr, U64 size) {
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value = ih.mmio_read(index);
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return value;
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}
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else if (SMU_MMIO.contains(index)) {
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value = smu.mmio_read(index);
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return value;
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}
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else if (SAM_MMIO.contains(index)) {
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value = sam.mmio_read(index);
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return value;
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}
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else if (SMU_MMIO.contains(index)) {
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value = smu.mmio_read(index);
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return value;
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}
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switch (index) {
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// ACP
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@ -160,18 +160,30 @@ U64 LiverpoolGCDevice::mmio_read(U64 addr, U64 size) {
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value = 0xFFFFFFFF;
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break;
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// BIF
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case mmBIF_FB_EN:
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case mmBIOS_SCRATCH_7:
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case mmGARLIC_FLUSH_CNTL:
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case mmCC_BIF_SECURE_CNTL:
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break;
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// GCA
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case mmGRBM_GFX_INDEX:
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case mmRLC_MAX_PG_CU:
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case mmRLC_PG_CNTL:
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value = mmio[index];
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// OSS
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case mmSRBM_CNTL:
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case mmHDP_ADDR_CONFIG:
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case mmSEM_CHICKEN_BITS:
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case mmHDP_HOST_PATH_CNTL:
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break;
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case mmCP_HQD_ACTIVE:
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value = 0;
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break;
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case mmRLC_SERDES_CU_MASTER_BUSY:
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value = 0;
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// Unknown registers
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case 0x13E:
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case 0x1D0:
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case 0x615:
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case 0x618:
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case 0x619:
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case 0x61B:
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case 0x3BD3:
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case 0x3BD4:
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case 0x3BD5:
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break;
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default:
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@ -206,14 +218,14 @@ void LiverpoolGCDevice::mmio_write(U64 addr, U64 value, U64 size) {
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ih.mmio_write(index, value);
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return;
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}
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else if (SMU_MMIO.contains(index)) {
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smu.mmio_write(index, value);
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return;
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}
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else if (SAM_MMIO.contains(index)) {
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sam.mmio_write(index, value);
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return;
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}
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else if (SMU_MMIO.contains(index)) {
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smu.mmio_write(index, value);
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return;
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}
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// Indirect registers
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switch (index) {
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@ -230,87 +242,43 @@ void LiverpoolGCDevice::mmio_write(U64 addr, U64 value, U64 size) {
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mmio[mmACP_SOFT_RESET] = (value << 16);
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break;
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// GCA
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case mmGRBM_GFX_INDEX:
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case mmRLC_PG_ALWAYS_ON_CU_MASK:
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case mmRLC_MAX_PG_CU:
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case mmRLC_PG_CNTL:
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// OSS
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case mmSRBM_CNTL:
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break;
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case mmSRBM_GFX_CNTL:
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DPRINTF("mmSRBM_GFX_CNTL { me: %d, pipe: %d, queue: %d, vmid: %d }",
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REG_GET_FIELD(value, SRBM_GFX_CNTL, MEID),
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REG_GET_FIELD(value, SRBM_GFX_CNTL, PIPEID),
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REG_GET_FIELD(value, SRBM_GFX_CNTL, QUEUEID),
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REG_GET_FIELD(value, SRBM_GFX_CNTL, VMID));
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break;
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// GMC
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case mmMC_SHARED_BLACKOUT_CNTL:
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case mmMC_SEQ_RESERVE_0_S:
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case mmMC_SEQ_RESERVE_1_S:
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case mmMC_RPB_ARB_CNTL:
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case mmMC_RPB_CID_QUEUE_WR:
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case mmMC_RPB_WR_COMBINE_CNTL:
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case mmMC_RPB_DBG1:
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case mmMC_HUB_WDP_IH:
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case mmMC_HUB_WDP_CPF:
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case mmMC_HUB_RDREQ_CPC:
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case mmMC_HUB_WDP_RLC:
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case mmMC_HUB_RDREQ_UVD:
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case mmMC_HUB_WRRET_MCDW:
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case mmMC_HUB_RDREQ_DMIF:
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case mmMC_HUB_RDREQ_CNTL:
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case mmMC_HUB_RDREQ_MCDW:
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case mmMC_HUB_RDREQ_MCDX:
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case mmMC_HUB_RDREQ_MCDY:
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case mmMC_HUB_RDREQ_MCDZ:
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case mmMC_CITF_CREDITS_ARB_RD:
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case mmMC_CITF_CREDITS_ARB_WR:
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case mmMC_RD_GRP_EXT:
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case mmMC_WR_GRP_EXT:
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case mmMC_RD_GRP_LCL:
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case mmMC_WR_GRP_LCL:
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case mmMC_ARB_TM_CNTL_RD:
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case mmMC_ARB_TM_CNTL_WR:
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case mmMC_ARB_LAZY0_RD:
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case mmMC_ARB_LAZY0_WR:
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case mmMC_ARB_AGE_RD:
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case mmMC_ARB_AGE_WR:
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case mmMC_RD_GRP_GFX:
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case mmMC_WR_GRP_GFX:
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case mmMC_RD_GRP_SYS:
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case mmMC_WR_GRP_SYS:
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case mmMC_RD_GRP_OTH:
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case mmMC_WR_GRP_OTH:
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case mmMC_HUB_RDREQ_CPF:
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case mmMC_HUB_WDP_ACPO:
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case mmMC_ARB_WTM_CNTL_WR:
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case mmMC_HUB_RDREQ_VMC:
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case mmMC_ARB_WTM_CNTL_RD:
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case mmMC_ARB_RET_CREDITS_WR:
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case mmMC_ARB_LM_WR:
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case mmMC_ARB_LM_RD:
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case mmMC_ARB_RET_CREDITS_RD:
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case mmMC_HUB_WDP_VCEU:
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case mmMC_HUB_WDP_XDMAM:
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case mmMC_HUB_WDP_XDMA:
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case mmMC_HUB_RDREQ_XDMAM:
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case mmMC_ARB_RET_CREDITS2:
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case mmMC_SHARED_CHMAP:
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case mmMC_ARB_SQM_CNTL:
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case mmMC_BIST_MISMATCH_ADDR:
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case mmMC_XPB_CLK_GAT:
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case mmMC_HUB_MISC_SIP_CG:
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case mmMC_HUB_MISC_HUB_CG:
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case mmMC_HUB_MISC_VM_CG:
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case mmMC_CITF_MISC_RD_CG:
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case mmMC_CITF_MISC_WR_CG:
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case mmMC_CITF_MISC_VM_CG:
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case mmVM_L2_CG:
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#ifdef NEEDSPORTING
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break;
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case mmCP_PFP_UCODE_DATA:
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liverpool_gc_ucode_load(s, mmCP_PFP_UCODE_ADDR, value);
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break;
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case mmCP_CE_UCODE_DATA:
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liverpool_gc_ucode_load(s, mmCP_CE_UCODE_ADDR, value);
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break;
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case mmCP_MEC_ME1_UCODE_DATA:
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liverpool_gc_ucode_load(s, mmCP_MEC_ME1_UCODE_ADDR, value);
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break;
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case mmCP_MEC_ME2_UCODE_DATA:
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liverpool_gc_ucode_load(s, mmCP_MEC_ME2_UCODE_ADDR, value);
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break;
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case mmRLC_GPM_UCODE_DATA:
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liverpool_gc_ucode_load(s, mmRLC_GPM_UCODE_ADDR, value);
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break;
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/* oss */
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case mmSDMA0_UCODE_DATA:
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liverpool_gc_ucode_load(s, mmSDMA0_UCODE_ADDR, value);
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break;
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case mmSDMA1_UCODE_DATA:
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liverpool_gc_ucode_load(s, mmSDMA1_UCODE_ADDR, value);
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break;
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#endif
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// Simple registers
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case mmSAM_IX_INDEX:
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case mmSAM_GPR_SCRATCH_0:
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case mmSAM_GPR_SCRATCH_1:
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case mmSAM_GPR_SCRATCH_2:
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case mmSAM_GPR_SCRATCH_3:
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break;
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default:
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DPRINTF("index=0x%llX, size=0x%llX, value=0x%llX }", index, size, value);
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assert_always("Unimplemented");
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@ -11,6 +11,7 @@
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*/
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#include "sam.h"
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#include "sam_regs.h"
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#include <orbital/hardware/liverpool/gmc/gmc.h>
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#include <orbital/hardware/liverpool/oss/ih.h>
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#include <orbital/hardware/liverpool/smu/smu.h>
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@ -40,6 +41,7 @@ SamDevice::SamDevice(GmcDevice& gmc, IhDevice& ih, SmuDevice& smu)
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void SamDevice::reset() {
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gpr.fill(0);
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ih_cpu_am32_int_ctx = 0;
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ih_cpu_am32_int_status = 0;
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ih_am32_cpu_int_ctx = 0;
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ix_data.fill(0);
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@ -61,15 +63,15 @@ U32 SamDevice::mmio_read(U32 index) {
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case ixSAM_IH_CPU_AM32_INT_CTX_LOW:
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value = ih_cpu_am32_int_ctx_low;
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break;
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case ixSAM_IH_CPU_AM32_INT_STATUS:
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value = ih_cpu_am32_int_status;
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break;
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case ixSAM_IH_AM32_CPU_INT_CTX_HIGH:
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value = ih_am32_cpu_int_ctx_high;
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break;
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case ixSAM_IH_AM32_CPU_INT_CTX_LOW:
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value = ih_am32_cpu_int_ctx_low;
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break;
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case ixSAM_IH_CPU_AM32_INT_STATUS:
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value = ih_cpu_am32_int_status;
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break;
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default:
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DPRINTF("mmSAM_IX_DATA_read { index: %X }", ix_index);
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value = ix_data[ix_index];
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@ -24,61 +24,6 @@ constexpr auto SAM_MMIO = OffsetRange(0x8800, 0x100);
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constexpr auto SAM0_MMIO = OffsetRange(0x8800, 0x100);
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constexpr auto SAM1_MMIO = OffsetRange(0x8900, 0x100);
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// SAMU
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#define mmSAM_IX_INDEX 0x8800
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#define mmSAM_IX_DATA 0x8801
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#define mmSAM_SAB_IX_INDEX 0x8802
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#define mmSAM_SAB_IX_DATA 0x8803
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#define mmSAM_IND_INDEX 0x8800
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#define mmSAM_IND_DATA 0x8801
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#define mmSAM_AM32_BOOT_BASE 0x8809
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#define mmSAM_AM32_BOOT_OFFSET 0x880A
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#define mmSAM_AM32_BOOT_LENGTH 0x880B
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#define mmSAM_AM32_BOOT_CTRL 0x880C
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#define mmSAM_AM32_BOOT_STATUS 0x880D
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#define mmSAM_AM32_BOOT_HASH0 0x880E
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#define mmSAM_AM32_BOOT_HASH1 0x880F
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#define mmSAM_AM32_BOOT_HASH2 0x8810
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#define mmSAM_AM32_BOOT_HASH3 0x8811
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#define mmSAM_AM32_BOOT_HASH4 0x8812
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#define mmSAM_AM32_BOOT_HASH5 0x8813
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#define mmSAM_AM32_BOOT_HASH6 0x8814
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#define mmSAM_AM32_BOOT_HASH7 0x8815
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#define mmSAM_EMU_SRCID 0x8816
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#define mmSAM_GPR_SCRATCH_4 0x8818
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#define mmSAM_GPR_SCRATCH_5 0x8819
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#define mmSAM_GPR_SCRATCH_6 0x881A
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#define mmSAM_GPR_SCRATCH_7 0x881B
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#define mmSAM_GPR_SCRATCH_0 0x881C
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#define mmSAM_GPR_SCRATCH_1 0x881D
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#define mmSAM_GPR_SCRATCH_2 0x881E
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#define mmSAM_GPR_SCRATCH_3 0x881F
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#define mmSAM_POWER_GATE 0x8834
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#define mmSAM_BOOT_PWR_UP 0x8835
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#define mmSAM_SMU_ALLOW_MEM_ACCESS 0x8836
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#define mmSAM_PGFSM_CONFIG_REG 0x8837
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#define mmSAM_PGFSM_WRITE_REG 0x8838
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#define mmSAM_PGFSM_READ_REG 0x8839
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#define mmSAM_PKI_FAIL_STATUS 0x883A
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// SAMU IX
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#define ixSAM_RST_HOST_SOFT_RESET 0x0001
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#define ixSAM_CGC_HOST_CTRL 0x0003
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#define ixSAM_IH_CPU_AM32_INT 0x0032
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#define ixSAM_IH_CPU_AM32_INT_CTX_HIGH 0x0033
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#define ixSAM_IH_CPU_AM32_INT_CTX_LOW 0x0034
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#define ixSAM_IH_AM32_CPU_INT_CTX_HIGH 0x0035
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#define ixSAM_IH_AM32_CPU_INT_CTX_LOW 0x0036
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#define ixSAM_IH_AM32_CPU_INT_ACK 0x0037
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#define ixSAM_UNK3E 0x003E
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#define ixSAM_IH_CPU_AM32_INT_STATUS 0x004A
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#define ixSAM_IH_AM32_CPU_INT_STATUS 0x004B
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#define ixSAM_RST_HOST_SOFT_RST_RDY 0x0051
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// SAMU SAB IX
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#define ixSAM_SAB_INIT_TLB_CONFIG 0x0004
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#define ixSAM_SAB_UNK29 0x0029
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/* SAMU Commands */
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struct samu_command_io_open_t {
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char name[8];
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73
src/orbital/hardware/liverpool/sam/sam_regs.h
Normal file
73
src/orbital/hardware/liverpool/sam/sam_regs.h
Normal file
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/**
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* AMD Secure Asset Management Unit (SAMU) device.
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*
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* Copyright 2017-2021. Orbital project.
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* Released under MIT license. Read LICENSE for more details.
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*
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* Authors:
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* - Alexandro Sanchez Bach <alexandro@phi.nz>
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*/
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#pragma once
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// SAM block
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#define mmSAM_IX_INDEX 0x8800
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#define mmSAM_IX_DATA 0x8801
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#define mmSAM_SAB_IX_INDEX 0x8802
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#define mmSAM_SAB_IX_DATA 0x8803
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#define mmSAM_IND_INDEX 0x8800
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#define mmSAM_IND_DATA 0x8801
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#define mmSAM_AM32_BOOT_BASE 0x8809
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#define mmSAM_AM32_BOOT_OFFSET 0x880A
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#define mmSAM_AM32_BOOT_LENGTH 0x880B
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#define mmSAM_AM32_BOOT_CTRL 0x880C
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#define mmSAM_AM32_BOOT_STATUS 0x880D
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#define mmSAM_AM32_BOOT_HASH0 0x880E
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#define mmSAM_AM32_BOOT_HASH1 0x880F
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#define mmSAM_AM32_BOOT_HASH2 0x8810
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#define mmSAM_AM32_BOOT_HASH3 0x8811
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#define mmSAM_AM32_BOOT_HASH4 0x8812
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#define mmSAM_AM32_BOOT_HASH5 0x8813
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#define mmSAM_AM32_BOOT_HASH6 0x8814
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#define mmSAM_AM32_BOOT_HASH7 0x8815
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#define mmSAM_EMU_SRCID 0x8816
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#define mmSAM_GPR_SCRATCH_4 0x8818
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#define mmSAM_GPR_SCRATCH_5 0x8819
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#define mmSAM_GPR_SCRATCH_6 0x881A
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#define mmSAM_GPR_SCRATCH_7 0x881B
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#define mmSAM_GPR_SCRATCH_0 0x881C
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#define mmSAM_GPR_SCRATCH_1 0x881D
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#define mmSAM_GPR_SCRATCH_2 0x881E
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#define mmSAM_GPR_SCRATCH_3 0x881F
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#define mmSAM_POWER_GATE 0x8834
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#define mmSAM_BOOT_PWR_UP 0x8835
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||||
#define mmSAM_SMU_ALLOW_MEM_ACCESS 0x8836
|
||||
#define mmSAM_PGFSM_CONFIG_REG 0x8837
|
||||
#define mmSAM_PGFSM_WRITE_REG 0x8838
|
||||
#define mmSAM_PGFSM_READ_REG 0x8839
|
||||
#define mmSAM_PKI_FAIL_STATUS 0x883A
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||||
|
||||
// SAMIND block
|
||||
#define ixSAM_RST_HOST_SOFT_RESET 0x0001
|
||||
#define ixSAM_CGC_HOST_CTRL 0x0003
|
||||
#define ixSAM_IH_CPU_AM32_INT 0x0032
|
||||
#define ixSAM_IH_CPU_AM32_INT_CTX_HIGH 0x0033
|
||||
#define ixSAM_IH_CPU_AM32_INT_CTX_LOW 0x0034
|
||||
#define ixSAM_IH_AM32_CPU_INT_CTX_HIGH 0x0035
|
||||
#define ixSAM_IH_AM32_CPU_INT_CTX_LOW 0x0036
|
||||
#define ixSAM_IH_AM32_CPU_INT_ACK 0x0037
|
||||
#define ixSAM_SCRATCH_0 0x0038
|
||||
#define ixSAM_SCRATCH_1 0x0039
|
||||
#define ixSAM_SCRATCH_2 0x003A
|
||||
#define ixSAM_SCRATCH_3 0x003B
|
||||
#define ixSAM_SCRATCH_4 0x003C
|
||||
#define ixSAM_SCRATCH_5 0x003D
|
||||
#define ixSAM_SCRATCH_6 0x003E
|
||||
#define ixSAM_SCRATCH_7 0x003F
|
||||
#define ixSAM_IH_CPU_AM32_INT_STATUS 0x004A
|
||||
#define ixSAM_IH_AM32_CPU_INT_STATUS 0x004B
|
||||
#define ixSAM_RST_HOST_SOFT_RST_RDY 0x0051
|
||||
|
||||
// SABIND block
|
||||
#define ixSAM_SAB_INIT_TLB_CONFIG 0x0004
|
||||
#define ixSAM_SAB_EFUSE_STATUS_CNTL 0x0029
|
Loading…
Reference in a new issue