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hardware/liverpool/sam: Add undocumented register names

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This commit is contained in:
Alexandro Sanchez Bach 2021-11-03 18:05:31 +01:00
parent 2584000558
commit 475c1b5201
3 changed files with 66 additions and 30 deletions
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15
src/orbital/hardware/liverpool/sam/sam.cpp
View file

@ -1,6 +1,8 @@
/**
* AMD Secure Asset Management Unit (SAMU) device.
*
* Based on research from: Alexey Kulaev (@flatz).
*
* Copyright 2017-2021. Orbital project.
* Released under MIT license. Read LICENSE for more details.
*
@ -65,6 +67,9 @@ U32 SamDevice::mmio_read(U32 index) {
case ixSAM_IH_AM32_CPU_INT_CTX_LOW:
value = ih_am32_cpu_int_ctx_low;
break;
case ixSAM_IH_CPU_AM32_INT_STATUS:
value = ih_cpu_am32_int_status;
break;
default:
DPRINTF("mmSAM_IX_DATA_read { index: %X }", ix_index);
value = ix_data[ix_index];
@ -120,7 +125,7 @@ void SamDevice::mmio_write(U32 index, U32 value) {
break;
case ixSAM_IH_AM32_CPU_INT_ACK:
//ix_data[ixSAM_IH_AM32_CPU_INT_STATUS] = 0;
ix_data[ixSAM_IH_CPU_AM32_INT_STATUS] = 0;
ih_cpu_am32_int_status = 0;
break;
default:
DPRINTF("mmSAM_IX_DATA_write { index: %X, value: %llX }", ix_index, value);
@ -184,8 +189,8 @@ void SamDevice::handle_request(U32 value) {
gpr[3] = 0;
break;
}
ix_data[ixSAM_IH_CPU_AM32_INT_STATUS] = 0;
ix_data[ixSAM_IH_AM32_CPU_INT_STATUS] |= 1;
ih_cpu_am32_int_status = 0;
ih_am32_cpu_int_status |= 1;
return;
}
else {
@ -202,8 +207,8 @@ void SamDevice::handle_request(U32 value) {
return;
}
#endif
ix_data[ixSAM_IH_CPU_AM32_INT_STATUS] = 0;//1
ix_data[ixSAM_IH_AM32_CPU_INT_STATUS] |= 1;
ih_cpu_am32_int_status = 0;//1
ih_am32_cpu_int_status |= 1;
ih.push_iv(0, IV_SRCID_SAM, 0 /* TODO */);
}
}

79
src/orbital/hardware/liverpool/sam/sam.h
View file

@ -1,7 +1,7 @@
/**
* AMD Secure Asset Management Unit (SAMU) device.
*
* Based on research from: Alexey Kulaev (flatz).
* Based on research from: Alexey Kulaev (@flatz).
*
* Copyright 2017-2021. Orbital project.
* Released under MIT license. Read LICENSE for more details.
@ -20,35 +20,64 @@ class GmcDevice;
class IhDevice;
class SmuDevice;
constexpr auto SAM_MMIO = OffsetRange(0x8800, 0x20);
constexpr auto SAM_MMIO = OffsetRange(0x8800, 0x100);
constexpr auto SAM0_MMIO = OffsetRange(0x8800, 0x100);
constexpr auto SAM1_MMIO = OffsetRange(0x8900, 0x100);
// SAMU
#define mmSAM_IX_INDEX 0x00008800
#define mmSAM_IX_DATA 0x00008801
#define mmSAM_SAB_IX_INDEX 0x00008802
#define mmSAM_SAB_IX_DATA 0x00008803
#define mmSAM_GPR_SCRATCH_0 0x0000881C
#define mmSAM_GPR_SCRATCH_1 0x0000881D
#define mmSAM_GPR_SCRATCH_2 0x0000881E
#define mmSAM_GPR_SCRATCH_3 0x0000881F
#define mmSAM_IX_INDEX 0x8800
#define mmSAM_IX_DATA 0x8801
#define mmSAM_SAB_IX_INDEX 0x8802
#define mmSAM_SAB_IX_DATA 0x8803
#define mmSAM_IND_INDEX 0x8800
#define mmSAM_IND_DATA 0x8801
#define mmSAM_AM32_BOOT_BASE 0x8809
#define mmSAM_AM32_BOOT_OFFSET 0x880A
#define mmSAM_AM32_BOOT_LENGTH 0x880B
#define mmSAM_AM32_BOOT_CTRL 0x880C
#define mmSAM_AM32_BOOT_STATUS 0x880D
#define mmSAM_AM32_BOOT_HASH0 0x880E
#define mmSAM_AM32_BOOT_HASH1 0x880F
#define mmSAM_AM32_BOOT_HASH2 0x8810
#define mmSAM_AM32_BOOT_HASH3 0x8811
#define mmSAM_AM32_BOOT_HASH4 0x8812
#define mmSAM_AM32_BOOT_HASH5 0x8813
#define mmSAM_AM32_BOOT_HASH6 0x8814
#define mmSAM_AM32_BOOT_HASH7 0x8815
#define mmSAM_EMU_SRCID 0x8816
#define mmSAM_GPR_SCRATCH_4 0x8818
#define mmSAM_GPR_SCRATCH_5 0x8819
#define mmSAM_GPR_SCRATCH_6 0x881A
#define mmSAM_GPR_SCRATCH_7 0x881B
#define mmSAM_GPR_SCRATCH_0 0x881C
#define mmSAM_GPR_SCRATCH_1 0x881D
#define mmSAM_GPR_SCRATCH_2 0x881E
#define mmSAM_GPR_SCRATCH_3 0x881F
#define mmSAM_POWER_GATE 0x8834
#define mmSAM_BOOT_PWR_UP 0x8835
#define mmSAM_SMU_ALLOW_MEM_ACCESS 0x8836
#define mmSAM_PGFSM_CONFIG_REG 0x8837
#define mmSAM_PGFSM_WRITE_REG 0x8838
#define mmSAM_PGFSM_READ_REG 0x8839
#define mmSAM_PKI_FAIL_STATUS 0x883A
// SAMU IX
#define ixSAM_RST_HOST_SOFT_RESET 0x00000001
#define ixSAM_CGC_HOST_CTRL 0x00000003
#define ixSAM_IH_CPU_AM32_INT 0x00000032
#define ixSAM_IH_CPU_AM32_INT_CTX_HIGH 0x00000033
#define ixSAM_IH_CPU_AM32_INT_CTX_LOW 0x00000034
#define ixSAM_IH_AM32_CPU_INT_CTX_HIGH 0x00000035
#define ixSAM_IH_AM32_CPU_INT_CTX_LOW 0x00000036
#define ixSAM_IH_AM32_CPU_INT_ACK 0x00000037
#define ixSAM_UNK3E 0x0000003E
#define ixSAM_IH_CPU_AM32_INT_STATUS 0x0000004A
#define ixSAM_IH_AM32_CPU_INT_STATUS 0x0000004B
#define ixSAM_RST_HOST_SOFT_RST_RDY 0x00000051
#define ixSAM_RST_HOST_SOFT_RESET 0x0001
#define ixSAM_CGC_HOST_CTRL 0x0003
#define ixSAM_IH_CPU_AM32_INT 0x0032
#define ixSAM_IH_CPU_AM32_INT_CTX_HIGH 0x0033
#define ixSAM_IH_CPU_AM32_INT_CTX_LOW 0x0034
#define ixSAM_IH_AM32_CPU_INT_CTX_HIGH 0x0035
#define ixSAM_IH_AM32_CPU_INT_CTX_LOW 0x0036
#define ixSAM_IH_AM32_CPU_INT_ACK 0x0037
#define ixSAM_UNK3E 0x003E
#define ixSAM_IH_CPU_AM32_INT_STATUS 0x004A
#define ixSAM_IH_AM32_CPU_INT_STATUS 0x004B
#define ixSAM_RST_HOST_SOFT_RST_RDY 0x0051
// SAMU SAB IX
#define ixSAM_SAB_INIT_TLB_CONFIG 0x00000004
#define ixSAM_SAB_UNK29 0x00000029
#define ixSAM_SAB_INIT_TLB_CONFIG 0x0004
#define ixSAM_SAB_UNK29 0x0029
/* SAMU Commands */
struct samu_command_io_open_t {
@ -157,6 +186,8 @@ private:
U32 ix_index;
U32 sab_ix_index;
U32 ih_cpu_am32_int_status;
U32 ih_am32_cpu_int_status;
union {
LE<U64> ih_cpu_am32_int_ctx;
Bitfield<U64, 48, 16> ih_cpu_am32_int_flags;

2
src/orbital/hardware/liverpool/smu/smu.cpp
View file

@ -38,7 +38,7 @@
#define ixSMU_IOC_READ_0 0xC2100134
/**
* Clocks Domains:
* Clocks:
* - SCLK: ???
* - LCLK: ???
* - DCLK: UVD D-clock