Add more details to EmulatedException.

This commit is contained in:
Paul Holden 2023-11-18 17:31:28 +00:00
parent 38d841b876
commit 3c4349934f
2 changed files with 14 additions and 7 deletions

View file

@ -2,4 +2,11 @@
// EmulatedException interrupts processing of an instruction // EmulatedException interrupts processing of an instruction
// and prevents state (such as memory or registers) being updated. // and prevents state (such as memory or registers) being updated.
export class EmulatedException { export class EmulatedException {
constructor(msg) {
this.msg = msg;
}
toString() {
return this.msg;
}
} }

View file

@ -1183,14 +1183,14 @@ export class CPU0 {
const tlb = this.tlbFindEntry(address); const tlb = this.tlbFindEntry(address);
if (!tlb) { if (!tlb) {
this.raiseTLBException(UT_VEC, cpu0reg.causeExcCodeTLBL, address); this.raiseTLBException(UT_VEC, cpu0reg.causeExcCodeTLBL, address);
throw new EmulatedException(); throw new EmulatedException('TLBL UT_VEC');
} }
const odd = address & tlb.checkbit; const odd = address & tlb.checkbit;
const entryLo = odd ? tlb.pfno : tlb.pfne; const entryLo = odd ? tlb.pfno : tlb.pfne;
if ((entryLo & TLBLO_V) === 0) { if ((entryLo & TLBLO_V) === 0) {
this.raiseTLBException(E_VEC, cpu0reg.causeExcCodeTLBL, address); this.raiseTLBException(E_VEC, cpu0reg.causeExcCodeTLBL, address);
throw new EmulatedException(); throw new EmulatedException('TLBL E_VEC');
} }
const phys = odd ? tlb.physOdd : tlb.physEven; const phys = odd ? tlb.physOdd : tlb.physEven;
@ -1202,18 +1202,18 @@ export class CPU0 {
const tlb = this.tlbFindEntry(address); const tlb = this.tlbFindEntry(address);
if (!tlb) { if (!tlb) {
this.raiseTLBException(UT_VEC, cpu0reg.causeExcCodeTLBS, address); this.raiseTLBException(UT_VEC, cpu0reg.causeExcCodeTLBS, address);
throw new EmulatedException(); throw new EmulatedException('TLBS UT_VEC');
} }
const odd = address & tlb.checkbit; const odd = address & tlb.checkbit;
const entryLo = odd ? tlb.pfno : tlb.pfne; const entryLo = odd ? tlb.pfno : tlb.pfne;
if ((entryLo & TLBLO_V) === 0) { if ((entryLo & TLBLO_V) === 0) {
this.raiseTLBException(E_VEC, cpu0reg.causeExcCodeTLBS, address); this.raiseTLBException(E_VEC, cpu0reg.causeExcCodeTLBS, address);
throw new EmulatedException(); throw new EmulatedException('TLBS E_VEC');
} }
if ((entryLo & TLBLO_D) === 0) { if ((entryLo & TLBLO_D) === 0) {
this.raiseTLBException(E_VEC, cpu0reg.causeExcCodeMod, address); this.raiseTLBException(E_VEC, cpu0reg.causeExcCodeMod, address);
throw new EmulatedException(); throw new EmulatedException('Mod E_VEC');
} }
const phys = odd ? tlb.physOdd : tlb.physEven; const phys = odd ? tlb.physOdd : tlb.physEven;
@ -1223,12 +1223,12 @@ export class CPU0 {
unalignedLoad(address) { unalignedLoad(address) {
this.raiseAdELException(address); this.raiseAdELException(address);
throw new EmulatedException(); throw new EmulatedException('AdEL load');
} }
unalignedStore(address) { unalignedStore(address) {
this.raiseAdESException(address); this.raiseAdESException(address);
throw new EmulatedException(); throw new EmulatedException('AdES store');
} }
execBreakpoint() { execBreakpoint() {