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Author SHA1 Message Date
Dillon Beliveau
71c50af370 use same new timing code in the interpreter as the jit 2020-12-08 01:58:30 -05:00
Dillon Beliveau
771a609f6c abs.s and abs.d 2020-12-08 01:46:19 -05:00
Dillon Beliveau
5bef1fb883 RSP features and stubbing to make OoT happy 2020-12-08 01:33:07 -05:00
Dillon Beliveau
0d6352f5ef 4x upscaling by default 2020-12-08 01:09:20 -05:00
Dillon Beliveau
0ec6003d02 fix tests 2020-12-08 01:09:05 -05:00
Dillon Beliveau
4db1d5faff don't need to check when FR changes 2020-12-08 00:59:48 -05:00
Dillon Beliveau
dcc89660c0 register access functions to own header 2020-12-08 00:59:07 -05:00
Dillon Beliveau
f09b7a3c04 checks for 64 bit addressing enabled and leaving kernel mode 2020-12-08 00:34:24 -05:00
Dillon Beliveau
7b5b267206 sign-extend linked PC 2020-12-08 00:33:28 -05:00
Dillon Beliveau
be12de010f correct initial value of CP0 status 2020-12-08 00:06:58 -05:00
Dillon Beliveau
4a06c3b594 correctly handle FPU register accesses 2020-12-07 23:17:04 -05:00
Dillon Beliveau
f08237518a commented out vulkan debug definition 2020-12-07 22:56:15 -05:00
Dillon Beliveau
25e269c722 new structure for holding FPRs 2020-12-07 22:55:11 -05:00
Dillon Beliveau
58bd80fc28 begin reworking FPU access functions 2020-12-07 22:47:00 -05:00
Dillon Beliveau
5c346cb746 DMTC1/DMFC1 2020-12-07 21:20:08 -05:00
Dillon Beliveau
356f6e97ad compile a new block from inside the handler 2020-12-06 11:51:23 -05:00
Dillon Beliveau
3f37439c53 latest version of parallel-rdp 2020-12-06 02:15:08 -05:00
Dillon Beliveau
cf46ada719 fix vulkan validation errors by ensuring images have the correct properties 2020-12-06 01:57:57 -05:00
Dillon Beliveau
6b68f130c0 RDRAM aligned to a page boundary 2020-12-06 01:40:13 -05:00
Dillon Beliveau
dc26afe88a let RDP plugin handle these, don't crash 2020-12-05 22:41:46 -05:00
Dillon Beliveau
38a8ffdabb more RSP instructions 2020-12-05 22:40:19 -05:00
Dillon Beliveau
2df63bd2e3 fix tests and cleanup 2020-12-05 21:56:42 -05:00
Dillon Beliveau
6f2503577e both left and right triggers work as Z buttons 2020-12-05 20:58:43 -05:00
Dillon Beliveau
ce741f13fb Don't check every single RSP cycle if an instruction needs to be decoded 2020-12-05 20:48:04 -05:00
Dillon Beliveau
58dd32d194 cleanup includes 2020-12-05 20:02:28 -05:00
Dillon Beliveau
bde41c7684 rework RSP timing 2020-12-05 20:00:09 -05:00
Dillon Beliveau
ec25c6357e load gamecontrollerdb.txt if it exists 2020-12-05 13:30:47 -05:00
Dillon Beliveau
0f5d33c5aa use a mutex to block the audio thread from accessing the audiostream while it's being recreated 2020-12-01 23:02:53 -05:00
Dillon Beliveau
0ad8a735c7 sanitizers commented out in cmakelists 2020-12-01 22:16:01 -05:00
Dillon Beliveau
b1988d9d34 fix more sanitizer-detected issues 2020-12-01 22:03:33 -05:00
Dillon Beliveau
164f6e6adb fix some UBSan errors 2020-12-01 20:05:13 -05:00
Dillon Beliveau
efc7e89872 use memcpy for memory accesses 2020-12-01 19:21:11 -05:00
Dillon Beliveau
1b72259f6b Use straight pointers 2020-11-30 22:55:03 -05:00
Dillon Beliveau
8286a58e6d support loading .v64 and .n64 byte-swapped files 2020-11-30 20:02:56 -05:00
Dillon Beliveau
a6b1715340 cleanup unreachable logfatals 2020-11-29 22:36:35 -05:00
Dillon Beliveau
dacd79030b helpful messages 2020-11-29 21:36:56 -05:00
Dillon Beliveau
3fcc79ee40 don't try to build tests if bass and chksum64 are not on the path 2020-11-29 21:35:51 -05:00
Dillon Beliveau
48a3c0941a return zero (and log a warning) when reading from some other cartridge domains 2020-11-29 21:01:14 -05:00
Dillon Beliveau
b38fd7b5c4 these instructions use broadcast modifiers in VT 2020-11-29 20:54:20 -05:00
Dillon Beliveau
43ab78a908 allow reading DMA_CACHE value from RSP CP0 2020-11-29 20:54:08 -05:00
Dillon Beliveau
90270a56cf various DMA fixes 2020-11-29 20:53:57 -05:00
Dillon Beliveau
2b2cd6f443 allow use of broadcast modifiers here 2020-11-29 20:16:06 -05:00
Dillon Beliveau
ca36909f01 read single bytes from AI registers 2020-11-29 20:15:41 -05:00
Dillon Beliveau
068595f29a misaligned RSP DMA reads are only warnings 2020-11-29 12:54:21 -05:00
Dillon Beliveau
b6ce54af91 SIMD-ify lane selection where e [8, 15] 2020-11-29 12:46:09 -05:00
Dillon Beliveau
ed948f3813 ignore remaining build dirs 2020-11-29 12:07:14 -05:00
Dillon Beliveau
f9c3bcf190 add a warning 2020-11-29 12:04:56 -05:00
Dillon Beliveau
5566e95ea9 move tas_movie code into frontend dir 2020-11-29 11:35:54 -05:00
Dillon Beliveau
b63651cb82 implement DSUBU 2020-11-28 16:42:41 -05:00
Dillon Beliveau
e50c46c9c0 DSRL + DSRL32 2020-11-28 16:33:10 -05:00