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Author	SHA1	Message	Date
Dillon Beliveau	f5303cb5a8	combine cells	2020-12-22 20:29:44 -05:00
Dillon Beliveau	11bba27c24	change theme and formatting of some tables	2020-12-22 19:38:36 -05:00
Dillon Beliveau	d9cc6edc9d	Every MIPS interface register documented	2020-12-22 00:53:16 -05:00
Dillon Beliveau	5f72ce7461	more MI docs	2020-12-22 00:42:41 -05:00
Dillon Beliveau	458ece5fe9	document one MI register	2020-12-22 00:14:02 -05:00
Dillon Beliveau	8e1bd59b04	back to interpreter for these tests	2020-12-21 20:33:50 -05:00
Dillon Beliveau	533e4a4294	JIT: dmult, dsra, bltzal	2020-12-21 19:46:59 -05:00
Dillon Beliveau	3ea6dde4a7	increment Count correctly in JIT	2020-12-21 19:31:46 -05:00
Dillon Beliveau	73560e4a0e	BAILZERO macro	2020-12-20 17:20:51 -05:00
Dillon Beliveau	36cd6af3f8	remove logs	2020-12-20 17:17:48 -05:00
Dillon Beliveau	b54e223e1c	sra	2020-12-20 17:11:09 -05:00
Dillon Beliveau	9d640f5a95	SEAX macro	2020-12-20 16:58:08 -05:00
Dillon Beliveau	6bcdc6b081	LOADRAX/SAVERAX macros	2020-12-20 16:54:19 -05:00
Dillon Beliveau	0146ae4361	sll/srl	2020-12-20 16:40:35 -05:00
Dillon Beliveau	e0c3f1ca3c	ori/xori	2020-12-20 16:32:13 -05:00
Dillon Beliveau	e0f89a4775	reorganize	2020-12-20 16:23:31 -05:00
Dillon Beliveau	74f5a832ab	faster compiler for andi	2020-12-20 16:16:56 -05:00
Dillon Beliveau	1122d6732c	fix warning	2020-12-20 16:16:48 -05:00
Dillon Beliveau	5ab318ae72	macroin' and fixin' - (d)addi(u) shouldn't write to r0	2020-12-20 16:06:35 -05:00
Dillon Beliveau	b75d08ac59	fix addi/addiu	2020-12-20 15:52:23 -05:00
Dillon Beliveau	a675c11fd0	test_rom uses dynarec	2020-12-20 15:52:10 -05:00
Dillon Beliveau	f0c19ba275	addi/addiu don't use handlers at all	2020-12-20 14:43:09 -05:00
Dillon Beliveau	df4364c000	always bounds-check ROM	2020-12-17 23:43:41 -05:00
Dillon Beliveau	8eae9a3dda	Function for releasing RSP semaphore	2020-12-17 23:42:58 -05:00
Dillon Beliveau	040bb6f0c6	Revert "don't queue samples if we already have a full second of audio available" ... This reverts commit eb6c41a592.	2020-12-13 17:45:16 -05:00
Dillon Beliveau	0d9d680cbb	latest version of parallel-rdp	2020-12-13 15:03:48 -05:00
Dillon Beliveau	8df492a53a	load pif rom if it exists	2020-12-13 15:03:41 -05:00
Dillon Beliveau	fdd544e75b	commented out definitions	2020-12-13 14:35:50 -05:00
Dillon Beliveau	55454cbad4	use MAIN_DEPENDENCY	2020-12-13 14:35:41 -05:00
Dillon Beliveau	3861a8e884	CMake updates to work with Ninja generator	2020-12-13 14:03:01 -05:00
Dillon Beliveau	20e3bb388b	better name	2020-12-13 13:50:35 -05:00
Dillon Beliveau	eb6c41a592	don't queue samples if we already have a full second of audio available	2020-12-13 13:49:51 -05:00
Dillon Beliveau	a20ad247ba	all macro compiles together	2020-12-13 13:23:10 -05:00
Dillon Beliveau	78ac1f50c8	better variable name to not confuse myself	2020-12-13 02:01:45 -05:00
Dillon Beliveau	cc87506698	reset cpu steps to zero to not run too many RSP steps when it's enabled after being disabled for a while	2020-12-13 01:40:08 -05:00
Dillon Beliveau	7509cb5410	timing tweaks in logtester	2020-12-13 01:38:16 -05:00
Dillon Beliveau	7f9abd4e9d	when CP1 disabled, don't execute the instruction at all	2020-12-13 01:36:53 -05:00
Dillon Beliveau	0c64e52422	eax and notes	2020-12-13 01:36:08 -05:00
Dillon Beliveau	a56a9594e5	use correct name	2020-12-13 01:35:58 -05:00
Dillon Beliveau	3f05940cbf	logtester updates to read jit sync logs	2020-12-12 23:52:36 -05:00
Dillon Beliveau	6db8562720	space	2020-12-12 23:52:02 -05:00
Dillon Beliveau	b9c440659f	optionally log jit sync points	2020-12-12 22:42:44 -05:00
Dillon Beliveau	73bca68855	more macros to cut down on LOC	2020-12-12 21:54:51 -05:00
Dillon Beliveau	bbaff5596a	cut down on a bit of code duplication with some macro use	2020-12-12 21:36:31 -05:00
Dillon Beliveau	6ea375b210	fix logging compilations	2020-12-12 21:18:48 -05:00
Dillon Beliveau	a6dade9566	LFV and SFV with bug warnings	2020-12-12 18:55:03 -05:00
Dillon Beliveau	060f46e4be	quiet down these logs	2020-12-12 18:47:18 -05:00
Dillon Beliveau	88a29fba2b	interpreter only: dmult, dsra, bltzal	2020-12-12 18:47:05 -05:00
Dillon Beliveau	3431c24ec5	DSRLV	2020-12-12 14:59:27 -05:00
Dillon Beliveau	45dfb97456	add correct amount to length	2020-12-12 14:57:17 -05:00