1647 commits

Author	SHA1	Message	Date
Dillon Beliveau	113ebb7114	cleanup VMOV	2021-01-03 20:34:53 -05:00
Dillon Beliveau	ec6fbecdb7	print out emu versions of res & accumulator	2021-01-03 19:46:13 -05:00
Dillon Beliveau	613cbddb8a	quiet down rsp fuzzer output	2021-01-03 17:55:04 -05:00
Dillon Beliveau	9046e0bc9e	RSP fuzzer configurable number of fuzzes per instruction, init state from hardware, comment out broken instructions	2021-01-03 17:19:34 -05:00
Dillon Beliveau	41964fef04	vnop is just a nop	2021-01-03 16:44:09 -05:00
Dillon Beliveau	0c1260c874	vnor works with non-zero element	2021-01-03 16:29:45 -05:00
Dillon Beliveau	5412ffb89a	vnand works with non-zero element	2021-01-03 16:24:45 -05:00
Dillon Beliveau	0e2030f039	comment out unimplemented instructions, remove unused function	2021-01-02 10:45:10 -05:00
Dillon Beliveau	c15003713a	link against core	2021-01-02 10:26:50 -05:00
Dillon Beliveau	eef74b6e47	automatically test each instruction 1000 times	2021-01-02 10:26:07 -05:00
Dillon Beliveau	c7e87bb865	send instruction to test over the wire	2021-01-02 09:28:10 -05:00
Dillon Beliveau	b57138d22f	fix VRSQ side effect	2020-12-31 17:57:28 -05:00
Dillon Beliveau	a99e2bcb70	colors in flag reg output	2020-12-31 16:54:28 -05:00
Dillon Beliveau	c61aa4a9cf	compare flag regs	2020-12-31 16:47:02 -05:00
Dillon Beliveau	b9888e7a8f	run infinite random tests from RSP fuzzer	2020-12-31 16:23:51 -05:00
Dillon Beliveau	4792e259e4	receive and verify flag registers	2020-12-31 16:13:05 -05:00
Dillon Beliveau	84425e17af	RSP fuzzer compares accumulator as well	2020-12-31 14:34:52 -05:00
Dillon Beliveau	048df5ccbf	first pass at an RSP fuzzer	2020-12-30 23:02:55 -05:00
Dillon Beliveau	17dc2b1f6e	quiet!	2020-12-29 17:00:35 -05:00
Dillon Beliveau	b8ade649cd	fix PI_DRAM_ADDR alignment	2020-12-29 14:51:39 -05:00
Dillon Beliveau	185160c1fd	get rid of dma.c/h	2020-12-29 14:37:28 -05:00
Dillon Beliveau	aefd7490fb	64 bit TLB, hopefully works	2020-12-29 13:57:01 -05:00
Dillon Beliveau	139ddfbebf	tlb fixes, prep for 64 bit TLB	2020-12-29 02:32:50 -05:00
Dillon Beliveau	1f8fec6dec	more 64 bit accesses, detect TLB operations in 64 bit mode	2020-12-28 19:50:26 -05:00
Dillon Beliveau	0c9783a73b	ll, sc	2020-12-28 19:30:06 -05:00
Dillon Beliveau	5fae26ef7b	XKPHYS	2020-12-28 19:25:14 -05:00
Dillon Beliveau	babd540ef9	SCD	2020-12-28 19:25:10 -05:00
Dillon Beliveau	0845fb6ef1	lld in interpreter	2020-12-28 18:37:49 -05:00
Dillon Beliveau	854805a585	ignore writes to cart_2_1	2020-12-28 18:24:06 -05:00
Dillon Beliveau	10238640e5	64 bit version of entry_hi	2020-12-28 18:23:54 -05:00
Dillon Beliveau	75ff5f2c64	allow reads from FCR0, with a warning	2020-12-28 18:11:16 -05:00
Dillon Beliveau	946e929506	tne in interpreter	2020-12-28 18:11:16 -05:00
Dillon Beliveau	f47948369e	return 0 for word reads from cart 1_3	2020-12-28 18:11:16 -05:00
Dillon Beliveau	c124a3596b	context and xcontext in 64 bit mode	2020-12-28 18:11:16 -05:00
Dillon Beliveau	05a0c81088	register size fixes	2020-12-28 18:11:16 -05:00
Dillon Beliveau	38947cbcb3	update some format strings for 64 bit addressing	2020-12-28 03:16:08 -05:00
Dillon Beliveau	8e47d4c784	latest version of parallel-rdp	2020-12-28 03:00:22 -05:00
Dillon Beliveau	095ef736fc	not sure why this was still here	2020-12-28 01:06:06 -05:00
Dillon Beliveau	a4304ddf36	c.un	2020-12-28 00:55:04 -05:00
Dillon Beliveau	2c25314dab	fix MI_VERSION_REG	2020-12-28 00:53:59 -05:00
Dillon Beliveau	6b991b50ff	probably incorrect c.ule	2020-12-28 00:32:05 -05:00
Dillon Beliveau	0a09de0365	daddiu doesn't throw overflow exceptions	2020-12-28 00:24:21 -05:00
Dillon Beliveau	8178bb7216	RDP command processing fixes	2020-12-28 00:15:56 -05:00
Dillon Beliveau	41d12a23f8	DMTC0/DMFC0	2020-12-27 17:11:37 -05:00
Dillon Beliveau	a858271685	don't crash on vsync of 0x20C	2020-12-27 12:59:38 -05:00
Dillon Beliveau	85e4fdfcad	split into own method	2020-12-27 12:28:00 -05:00
Dillon Beliveau	df3b120235	mask DRAM address in SI DMA	2020-12-27 02:15:06 -05:00
Dillon Beliveau	31936ecc2a	don't lower interrupts randomly	2020-12-27 02:14:57 -05:00
Dillon Beliveau	999562468c	mask Count reg	2020-12-27 02:14:49 -05:00
Dillon Beliveau	24e9d8f6cc	hack: write RDRAM size to 0x318 after first PI DMA	2020-12-27 02:14:28 -05:00