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1859 commits 16 branches 0 tags 17 MiB
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1066 commits

Author SHA1 Message Date
Dillon Beliveau
3b5a3b5634 CP1 NEG 2020-07-11 17:26:07 -04:00
Dillon Beliveau
4a2d4b1fbe some FPU instructions 2020-07-11 17:14:30 -04:00
Dillon Beliveau
596ccf8a99 RDP plugin may or may not raise an interrupt, so we should just check if it did instead of always raising one ourselves. 2020-07-11 16:43:29 -04:00
Dillon Beliveau
d47f4bb233 Lots more RSP instructions, quiet down logging 2020-07-11 03:41:16 -04:00
Dillon Beliveau
77eeb620da RSP: more instructions, hook up more interfaces, unaligned reads 2020-07-11 03:28:46 -04:00
Dillon Beliveau
10fd9722f4 Finish up RSP interrupts, hook up RSP CP0 to more stuff 2020-07-11 02:59:54 -04:00
Dillon Beliveau
bd30706876 RSP SUB 2020-07-11 02:59:20 -04:00
Dillon Beliveau
4fa2776234 RSP: SSV, reverse DMA 2020-07-11 02:51:48 -04:00
Dillon Beliveau
a74acbc850 RSP: VMACF, VMACU 2020-07-11 02:41:17 -04:00
Dillon Beliveau
b954cccb46 Vector registers in little endian byte order 2020-07-11 02:36:15 -04:00
Dillon Beliveau
dd7df9b1e5 RSP: CFC2, VMULF, VMULU, fix VSAR 2020-07-11 02:24:00 -04:00
Dillon Beliveau
5962fe68d3 uncomment 2020-07-09 23:22:23 -04:00
Dillon Beliveau
5d60958519 VU vec stuff, RSP SB 2020-07-09 23:13:57 -04:00
Dillon Beliveau
0d5b296207 RSP can only read from IMEM 2020-07-09 22:13:55 -04:00
Dillon Beliveau
f74b0f833c Lots of CP2 stubbin' 2020-07-09 21:30:43 -04:00
Dillon Beliveau
8a4d6f7e4c this is better named v 2020-07-09 19:30:15 -04:00
Dillon Beliveau
ba6e5e56eb LQV 2020-07-09 19:26:10 -04:00
Dillon Beliveau
00b3e66cda LDV/LSV 2020-07-09 19:17:46 -04:00
Dillon Beliveau
6796201a8d these decode differently 2020-07-08 23:38:33 -04:00
Dillon Beliveau
35f8b35a8b Stub LWC2 decodes 2020-07-08 23:16:18 -04:00
Dillon Beliveau
22e3a9f9a7 RSP semaphore, more RSP instructions 2020-07-08 23:05:42 -04:00
Dillon Beliveau
01af111a7b RSP ADD, BLEZ 2020-07-06 21:25:19 -04:00
Dillon Beliveau
a876e4d809 Load Mupen64Plus compatible RDP plugins 2020-07-06 21:18:43 -04:00
Dillon Beliveau
376f5ca5cd These instructions don't exist on the RSP 2020-07-05 15:48:07 -04:00
Dillon Beliveau
2af5431242 Tune up RSP IO, add RSP JR 2020-07-05 15:47:33 -04:00
Dillon Beliveau
3cf0f11277 RSP BNE, hook up first RSP CP0 register 2020-07-05 15:02:13 -04:00
Dillon Beliveau
f1521898b3 stub RSP CP0 2020-07-05 14:53:17 -04:00
Dillon Beliveau
dfd60504e1 more RSP instructions 2020-07-05 14:39:25 -04:00
Dillon Beliveau
73fa1e7230 RSP is more separate/different than I originally thought 2020-07-05 14:03:23 -04:00
Dillon Beliveau
6cb307d2d8 RSP is executing instructions 2020-07-05 12:50:42 -04:00
Dillon Beliveau
2ec80ad5fa RSP DMA should use RSP bus 2020-07-05 11:10:48 -04:00
Dillon Beliveau
c4d05af7ea Starting to get RSP running 2020-07-04 13:20:21 -04:00
Dillon Beliveau
273394a24f stubbing more RSP regs 2020-07-03 17:30:09 -04:00
Dillon Beliveau
dd1a578b82 SUB 2020-07-03 14:55:47 -04:00
Dillon Beliveau
eb3d12d51d working on TLB stuff 2020-07-03 14:48:28 -04:00
Dillon Beliveau
ab56575beb DDIVU, crash on divide by zero 2020-07-03 12:44:10 -04:00
Dillon Beliveau
9f705b050c Comment out variables that are unused (for now), DSRA32, DMULTU 2020-07-03 12:25:02 -04:00
Dillon Beliveau
b045df331c Fix LWL/LWR instructions. Several small tweaks. Input should work now 2020-07-02 23:08:01 -04:00
Dillon Beliveau
f6154f1cc5 CPU tests are file based 2020-06-29 23:16:04 -04:00
Dillon Beliveau
5137e8772a More tests 2020-06-28 12:25:13 -04:00
Dillon Beliveau
1a4a8b9ce3 DSLLV 2020-06-27 22:54:03 -04:00
Dillon Beliveau
103e85bc68 c_sub 2020-06-27 13:34:01 -04:00
Dillon Beliveau
06e8cd0d3f c_lt 2020-06-27 13:28:26 -04:00
Dillon Beliveau
055c2829d1 Fix 16 bit graphics. Begin implementing controllers 2020-06-27 01:22:34 -04:00
Dillon Beliveau
ddd09844d0 Fix bugs, add instructions, add restrictions to CP0 writes 2020-06-25 00:42:40 -04:00
Dillon Beliveau
b1f1810003 Fix sign extension bug 2020-06-24 21:31:38 -04:00
Dillon Beliveau
920cb73080 Fix SH 2020-06-24 00:45:20 -04:00
Dillon Beliveau
3ab4224fb6 Quieter logs 2020-06-24 00:15:29 -04:00
Dillon Beliveau
8d24c34f1b less messy 2020-06-23 22:20:12 -04:00
Dillon Beliveau
106800e23e Fix LWL/LWR/SWL/SWR 2020-06-23 22:19:50 -04:00