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Author	SHA1	Message	Date
Dillon Beliveau	f2c1911776	upload n64-qt.exe	2023-07-09 15:05:56 -04:00
Dillon Beliveau	0c6d6ae0d0	update install-qt-action to v3	2023-07-09 12:42:34 -04:00
Dillon Beliveau	7c3af909ee	Merge branch 'dynarec_v2' into microsoft-abi	2023-07-09 00:20:47 -04:00
Dillon Beliveau	a925ba7e76	fix dangling pointer for compiler v1 and rsp	2023-07-09 00:20:24 -04:00
Dillon Beliveau	c122f9df3e	Windows support for dynarec v2 using the MS ABI	2023-07-08 18:03:29 -04:00
Dillon Beliveau	3a51ada83f	mtc0 CONFIG, DMTC0 ENTRY_LO0 & ENTRY_LO1	2023-06-05 22:12:39 -07:00
Dillon Beliveau	899209351a	scd, teq, tge, tgeu, tlt, tltu, tne	2023-05-29 17:28:24 -07:00
Dillon Beliveau	6e0caa7af1	read PRId	2023-05-29 17:09:17 -07:00
Dillon Beliveau	4c6eae6915	u64 and s64 multiply	2023-05-29 17:07:54 -07:00
Dillon Beliveau	878325ff70	correctly flush fpu registers	2023-05-27 20:01:11 -07:00
Dillon Beliveau	35ccca624f	allow MTC0 watchlo in the jit	2023-05-27 16:01:59 -07:00
Dillon Beliveau	e55c144fad	various jit fixes	2023-05-27 15:56:12 -07:00
Dillon Beliveau	6d66573bad	Merge branch 'master' into dynarec_v2	2023-05-19 17:40:02 -07:00
Dillon Beliveau	6502f7d2f1	Fix two implicit fallthrough errors	2023-05-18 23:16:20 -07:00
Dillon Beliveau	44024f14f7	Merge pull request #42 from OFFTKP/master ... Eliminate evil implicit fallthrough	2023-05-19 02:15:49 -04:00
offtkp	725c10e1fb	Eliminate evil implicit fallthrough	2023-05-19 00:45:12 +03:00
Dillon Beliveau	553e3d3eda	better constant propagation for multiplies and divides	2023-05-13 15:56:12 -07:00
Dillon Beliveau	02caf5560d	interrupts on the scheduler	2023-05-13 14:29:14 -07:00
Dillon Beliveau	d7576b4379	Merge pull request #41 from OFFTKP/master ... Support reading of ADDR_VI_H_START_REG	2023-05-03 17:03:44 -04:00
offtkp	db288ef0cb	Support reading of ADDR_VI_H_START_REG ... The libdragon example test roms read from this register during initialization	2023-05-03 17:38:53 +03:00
Dillon Beliveau	a31d7489cc	Merge branch 'master' into dynarec_v2	2023-04-29 14:12:01 -07:00
Dillon Beliveau	8b9dccfdaa	VI timing on scheduler	2023-04-29 14:04:54 -07:00
Dillon Beliveau	34d00d15f6	Merge branch 'master' into dynarec_v2	2023-04-29 11:16:33 -07:00
Dillon Beliveau	41708b9350	recording demos	2023-04-29 11:16:16 -07:00
Dillon Beliveau	6b7ed7941c	Get register type properly	2023-04-23 19:22:31 -07:00
Dillon Beliveau	f76ad08062	CP0 regs + TLB instructions, enough to get GoldenEye working	2023-04-23 16:28:53 -07:00
Dillon Beliveau	f37d9fc568	Sort block list so matching sysconfig is at the head when a miss occurs	2023-04-18 22:41:57 -07:00
Dillon Beliveau	1b3e930857	spilled support for xor imm	2023-04-16 15:49:20 -07:00
Dillon Beliveau	a79631314e	remove breakpoint	2023-04-16 15:05:52 -07:00
Dillon Beliveau	2465812502	fix a bug in DIV	2023-04-16 14:44:54 -07:00
Dillon Beliveau	b9801847ed	dynarec compare fixes + support for tas movies	2023-04-16 14:44:46 -07:00
Dillon Beliveau	ce598123d0	cop1 unusable exceptions are implemented in the jit now	2023-04-15 12:23:07 -07:00
Dillon Beliveau	8c81117c73	more float conversions	2023-04-15 12:17:49 -07:00
Dillon Beliveau	01b41aaeda	detect and handle branch in branch delay slot	2023-04-09 15:43:43 -07:00
Dillon Beliveau	73f234b76a	implement more MFC0 and DMFC0 registers	2023-04-09 15:24:53 -07:00
Dillon Beliveau	bc2c546668	compare u32 immediate fixes	2023-04-09 15:24:30 -07:00
Dillon Beliveau	a43437f63e	division improvements	2023-04-09 15:24:19 -07:00
Dillon Beliveau	bba290b97e	spilled reg handling in shifts	2023-04-09 15:22:30 -07:00
Dillon Beliveau	801c697bf6	dsrav	2023-04-09 15:11:39 -07:00
Dillon Beliveau	125e799ef9	set prev_branch = branch before handling TLB miss pc exception	2023-04-09 12:49:40 -07:00
Dillon Beliveau	ff51ff3ad7	pass bus access correctly during constant propagation (even though it shouldn't matter)	2023-04-09 12:36:48 -07:00
Dillon Beliveau	f5898fff12	check mult hi and mult lo in dynarec compare	2023-04-09 12:22:22 -07:00
Dillon Beliveau	ef5b74aca6	FPU register behavior improvements	2023-04-09 12:22:04 -07:00
Dillon Beliveau	52530fb466	lld	2023-04-09 10:29:43 -07:00
Dillon Beliveau	cf35a1d482	spilled reg handling in not_reg and add_reg_imm	2023-04-09 10:18:09 -07:00
Dillon Beliveau	40a95f83b5	ll, sc, improve conditional block exit instruction,	2023-04-08 17:31:28 -07:00
Dillon Beliveau	1a1ef04953	s64 multiply	2023-04-08 13:23:59 -07:00
Dillon Beliveau	59b37f750e	unordered float compares, dsrlv, teq	2023-04-08 10:48:14 -07:00
Dillon Beliveau	6309dfa002	set epc, xcontext, and implement dmfc0	2023-03-27 18:04:50 -07:00
Dillon Beliveau	0d1e7cf3e7	interpreter fallback when a delay slot is on a different page from its branch	2023-03-27 18:04:08 -07:00