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Author SHA1 Message Date
Dillon Beliveau
2a2de4ca4d LSV 2020-07-12 23:00:03 -04:00
Dillon Beliveau
8afd5e8047 ADDU and ADDIU are just ADD and ADDI in the RSP 2020-07-12 22:47:56 -04:00
Dillon Beliveau
c46d43f5d3 Make the text output nicer 2020-07-12 22:43:55 -04:00
Dillon Beliveau
716487e001 Housekeeping 2020-07-12 22:05:42 -04:00
Dillon Beliveau
21ef0712a9 fix SQV 2020-07-12 22:02:13 -04:00
Dillon Beliveau
2f9416b0f1 Display expected/actual test output 2020-07-12 22:00:36 -04:00
Dillon Beliveau
f5921e18d4 Still not perfect, but improve LQV and SQV 2020-07-12 21:48:17 -04:00
Dillon Beliveau
fde4ab30e2 This should be a 32 bit conversion 2020-07-12 21:44:41 -04:00
Dillon Beliveau
4cd1827209 TLB WIP 2020-07-12 18:03:27 -04:00
Dillon Beliveau
d098b80806 RSP unaligned word reads 2020-07-12 17:48:58 -04:00
Dillon Beliveau
4a3ec2c185 VAND, VNAND, VNOR, VNXOR, VOR, VXOR 2020-07-12 17:48:37 -04:00
Dillon Beliveau
51f9064f3f Improve LQV and SQV, not perfect yet though 2020-07-12 17:47:53 -04:00
Dillon Beliveau
249b14b849 no need to mask twice 2020-07-12 17:42:31 -04:00
Dillon Beliveau
7d53611e9f Convert expected value to little endian 2020-07-12 17:33:24 -04:00
Dillon Beliveau
74bf20656c Fix unaligned word writes 2020-07-12 17:31:23 -04:00
Dillon Beliveau
c6206d14b4 check test output 2020-07-12 16:29:54 -04:00
Dillon Beliveau
bc690f1e2e RSP LUI 2020-07-12 16:05:04 -04:00
Dillon Beliveau
64b36ecb2b RSP tests with autogenerated CMake configs and input data 2020-07-12 15:46:58 -04:00
Dillon Beliveau
6c6f5b2780 Add testcases for RSP 2020-07-12 14:36:42 -04:00
Dillon Beliveau
9031d91ae0 CPU test cases in cpu subdir 2020-07-12 12:52:41 -04:00
Dillon Beliveau
f50aededc6 Fix VSAR 2020-07-12 12:06:55 -04:00
Dillon Beliveau
9dc8409c96 Check RDP interrupts from the callback only 2020-07-11 23:49:00 -04:00
Dillon Beliveau
ca0a80d163 RSP unaligned word writes 2020-07-11 20:43:52 -04:00
Dillon Beliveau
7401ea7579 VMADH/VMADN 2020-07-11 20:43:32 -04:00
Dillon Beliveau
01e4426194 VMADL, VMADM, VMUDH 2020-07-11 19:00:15 -04:00
Dillon Beliveau
afc9fa84dd RSP SBV 2020-07-11 17:26:52 -04:00
Dillon Beliveau
3b5a3b5634 CP1 NEG 2020-07-11 17:26:07 -04:00
Dillon Beliveau
4a2d4b1fbe some FPU instructions 2020-07-11 17:14:30 -04:00
Dillon Beliveau
596ccf8a99 RDP plugin may or may not raise an interrupt, so we should just check if it did instead of always raising one ourselves. 2020-07-11 16:43:29 -04:00
Dillon Beliveau
d47f4bb233 Lots more RSP instructions, quiet down logging 2020-07-11 03:41:16 -04:00
Dillon Beliveau
77eeb620da RSP: more instructions, hook up more interfaces, unaligned reads 2020-07-11 03:28:46 -04:00
Dillon Beliveau
10fd9722f4 Finish up RSP interrupts, hook up RSP CP0 to more stuff 2020-07-11 02:59:54 -04:00
Dillon Beliveau
bd30706876 RSP SUB 2020-07-11 02:59:20 -04:00
Dillon Beliveau
4fa2776234 RSP: SSV, reverse DMA 2020-07-11 02:51:48 -04:00
Dillon Beliveau
5bd0f5e9a1 Don't need to set render scale 2020-07-11 02:41:35 -04:00
Dillon Beliveau
a74acbc850 RSP: VMACF, VMACU 2020-07-11 02:41:17 -04:00
Dillon Beliveau
b954cccb46 Vector registers in little endian byte order 2020-07-11 02:36:15 -04:00
Dillon Beliveau
dd7df9b1e5 RSP: CFC2, VMULF, VMULU, fix VSAR 2020-07-11 02:24:00 -04:00
Dillon Beliveau
5962fe68d3 uncomment 2020-07-09 23:22:23 -04:00
Dillon Beliveau
5d60958519 VU vec stuff, RSP SB 2020-07-09 23:13:57 -04:00
Dillon Beliveau
0d5b296207 RSP can only read from IMEM 2020-07-09 22:13:55 -04:00
Dillon Beliveau
f74b0f833c Lots of CP2 stubbin' 2020-07-09 21:30:43 -04:00
Dillon Beliveau
8a4d6f7e4c this is better named v 2020-07-09 19:30:15 -04:00
Dillon Beliveau
ba6e5e56eb LQV 2020-07-09 19:26:10 -04:00
Dillon Beliveau
00b3e66cda LDV/LSV 2020-07-09 19:17:46 -04:00
Dillon Beliveau
6796201a8d these decode differently 2020-07-08 23:38:33 -04:00
Dillon Beliveau
35f8b35a8b Stub LWC2 decodes 2020-07-08 23:16:18 -04:00
Dillon Beliveau
22e3a9f9a7 RSP semaphore, more RSP instructions 2020-07-08 23:05:42 -04:00
Dillon Beliveau
f047f5b89b Angrylion working for software renderer 2020-07-08 20:42:45 -04:00
Dillon Beliveau
0019e0170c Save my ears a bit 2020-07-07 21:09:11 -04:00