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Author SHA1 Message Date
Dillon Beliveau
5800fa4b73 BLTZ, BLTZL, MOV.S, MOV.D, JALR 2020-06-22 21:00:36 -04:00
Dillon Beliveau
50882d8f8d LWU, fix interrupts, mock AI status reg 2020-06-22 20:44:07 -04:00
Dillon Beliveau
4b4e8e8f5c Fix sign extension 2020-06-22 18:59:27 -04:00
Dillon Beliveau
f4377266fb each instruction takes two cycles 2020-06-22 18:41:01 -04:00
Dillon Beliveau
115f7646c3 interrupt tweaks 2020-06-22 18:34:34 -04:00
Dillon Beliveau
96960cf16e Make RDRAM 8MB 2020-06-21 22:43:51 -04:00
Dillon Beliveau
882f1cfcb7 Fix TRUNC, fix printf tokens 2020-06-21 15:01:13 -04:00
Dillon Beliveau
b42f4aca15 <Good commit message> 2020-06-21 05:33:39 -04:00
Dillon Beliveau
c53b3d6f12 Stub out args for float instructions too 2020-06-21 03:01:20 -04:00
Dillon Beliveau
a467eb0ded more FPU stubbin, C_LE, BC1T, BC1F 2020-06-21 03:00:08 -04:00
Dillon Beliveau
dd61f34401 Oops 2020-06-21 02:42:41 -04:00
Dillon Beliveau
308695f4c5 Instruction decoding fixes, FPU stuff 2020-06-21 02:42:03 -04:00
Dillon Beliveau
89d2a7a642 interrupts, exceptions, more instructions, logtester initializes registers to ares' values, etc etc 2020-06-21 00:07:59 -04:00
Dillon Beliveau
e2e3b0fd3f First floating point opcodes: mul.s and mul.d 2020-06-20 00:29:57 -04:00
Dillon Beliveau
a4b92a03c2 More instructions, probably broken exception handling, floating point stuff 2020-06-18 22:18:58 -04:00
Dillon Beliveau
ddc0dc2cdb SH, SRA, 16 bit reads/writes 2020-06-18 20:25:43 -04:00
Dillon Beliveau
9b7c8406db New instructions, bug fixes, allowing access to more registers 2020-06-18 20:02:15 -04:00
Dillon Beliveau
6c0131390c CFC1, CTC1 2020-06-18 00:49:12 -04:00
Dillon Beliveau
0c941f8754 Redo how CP0 registers are stored, implement status register 2020-06-17 23:46:42 -04:00
Dillon Beliveau
8c16c4fe05 Fix coprocessor instruction decoding. MFC0 instruction implemented 2020-06-17 23:23:57 -04:00
Dillon Beliveau
ea896e7975 Doubleword adds 2020-06-17 23:00:00 -04:00
Dillon Beliveau
1d5b6d4da3 Show disassembly in level-2 decode functions too 2020-06-17 22:38:11 -04:00
Dillon Beliveau
5e76ba9e91 Load and store doublewords 2020-06-17 22:27:58 -04:00
Dillon Beliveau
814ec3550a Rename all MIPS32 stuff to just MIPS 2020-06-17 22:05:00 -04:00
Dillon Beliveau
bff8fa082c Fixing sign extension errors 2020-06-17 21:53:40 -04:00
Dillon Beliveau
c73ab53832 CP0 work, all instrs run with 64 bit registers 2020-06-17 21:30:44 -04:00
Dillon Beliveau
23f3f3febc .h files are C 2020-06-17 17:09:16 -04:00
Dillon Beliveau
b559ff39bc Disassemble as MIPS64 2020-06-16 23:37:58 -04:00
Dillon Beliveau
5a2d7f17b8 this doesn't exist 2020-06-16 23:29:44 -04:00
Dillon Beliveau
d3103526f5 Treat as signed 2020-06-16 23:18:13 -04:00
Dillon Beliveau
89fc2001ed disassemble if necessary 2020-06-16 20:16:43 -04:00
Dillon Beliveau
e720afb1cb Got basic graphics working! 2020-06-16 20:03:26 -04:00
Dillon Beliveau
86d229fc08 Stub V_CURRENT and rendering 2020-06-16 17:35:45 -04:00
Dillon Beliveau
e6550af905 J instruction 2020-06-16 17:10:13 -04:00
Dillon Beliveau
8b2fa51e8a BGTZ, read VI Registers 2020-06-16 00:54:32 -04:00
Dillon Beliveau
8ef3059c61 these should be logtrace 2020-06-16 00:42:56 -04:00
Dillon Beliveau
8d3d689efc LB 2020-06-16 00:39:50 -04:00
Dillon Beliveau
0f97a7b73d Stub PIF and VI stuff 2020-06-16 00:32:07 -04:00
Dillon Beliveau
ab2135a1cd PI status reg writes 2020-06-15 23:20:36 -04:00
Dillon Beliveau
da97800feb Stub SI regs, ignore word writes to audio interface regs 2020-06-15 23:15:15 -04:00
Dillon Beliveau
a19358789b Stubbing RSP 2020-06-15 22:54:47 -04:00
Dillon Beliveau
804b898210 Better naming 2020-06-15 21:19:28 -04:00
Dillon Beliveau
a5cea9b366 Prefix opcode functions with mips32_ 2020-06-15 21:14:27 -04:00
Dillon Beliveau
d4690e0ace BGEZAL 2020-06-15 20:50:32 -04:00
Dillon Beliveau
f4c6907977 More instructions, logging changes 2020-06-15 20:13:57 -04:00
Dillon Beliveau
758ad31b06 Reorganize, add DMAs 2020-06-15 18:25:26 -04:00
Dillon Beliveau
7028e6b81a Guess it doesn't work on MacOS yet 2020-06-15 17:40:59 -04:00
Dillon Beliveau
b85a0ab89c Missed a couple GBA -> N64 2020-06-15 17:37:13 -04:00
Dillon Beliveau
13022fd044 Github actions build on Linux/MacOS 2020-06-15 17:36:18 -04:00
Dillon Beliveau
d49e93dde7 Stub PI regs, implement the first one 2020-06-14 17:35:23 -04:00