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Author SHA1 Message Date
Dillon Beliveau
7abd67306d don't translate address twice 2021-02-07 14:00:01 -05:00
Dillon Beliveau
d61242ec74 working on swapping DMEM to little endian 2021-02-07 13:34:32 -05:00
Dillon Beliveau
2f9f261b3f typo 2021-02-06 21:32:47 -05:00
Dillon Beliveau
5ccee24981 move stuff around, RSP bus doesn't need whole system 2021-02-06 21:32:47 -05:00
Dillon Beliveau
a8db71cb1a delete some unused code 2021-02-06 21:32:47 -05:00
Dillon Beliveau
7a87019d46 take RSP as argument here 2021-02-06 21:32:47 -05:00
Dillon Beliveau
92bc5b6be4 per instruction, not per cycle 2021-02-06 14:47:31 -05:00
Dillon Beliveau
cad07882ca
Merge pull request #9 from wheremyfoodat/master 
Update PIF HLE documentation
 2021-02-06 09:33:32 -05:00
wheremyfoodat
c29ab936d7 Fixed sign extension of initial $t3 val 2021-02-06 14:07:48 +02:00
wheremyfoodat
3a8e77c5fa Update PIF doc 2021-02-06 13:32:57 +02:00
Dillon Beliveau
85bc8922b8 continue using big endian for RSP 2021-01-24 15:09:15 -05:00
Dillon Beliveau
942e67a34d rdram to little endian (cpu supported only), use mainline parallel-rdp 2021-01-24 14:58:27 -05:00
Dillon Beliveau
c246c36511 move stuff around, RSP bus doesn't need whole system 2021-01-24 13:22:50 -05:00
Dillon Beliveau
c0d22f5f78 delete some unused code 2021-01-24 13:05:44 -05:00
Dillon Beliveau
a9a1fedf8b take RSP as argument here 2021-01-24 12:50:14 -05:00
Dillon Beliveau
dfcd708978 const 2021-01-23 19:19:01 -05:00
Dillon Beliveau
5856ef7823 close button on imgui demo window 2021-01-23 13:44:28 -05:00
Dillon Beliveau
ccdb50728e update readme 2021-01-23 13:32:02 -05:00
Dillon Beliveau
9b02ea87fc add -h / --help parameter 2021-01-23 13:14:09 -05:00
Dillon Beliveau
fb9e659f42 Add screenshot 2021-01-23 12:59:10 -05:00
Dillon Beliveau
e3e8a4bc4c Remove screenshot 2021-01-23 12:58:01 -05:00
Dillon Beliveau
5c7c3c3ffe cleanup useless comments 2021-01-22 00:26:07 -05:00
Dillon Beliveau
087004f6bb
Merge pull request #8 from Dillonb/imgui 
Imgui
 2021-01-22 00:20:24 -05:00
Dillon Beliveau
f0e4dbc620 don't destroy these 2021-01-21 23:34:20 -05:00
Dillon Beliveau
ccdb94a97e use a renderpass, draw parallel-rdp's image to swapchain using a textured quad 2021-01-21 23:21:18 -05:00
Dillon Beliveau
bdb492bcc5 cleanup font upload code further 2021-01-20 18:03:27 -05:00
Dillon Beliveau
be327a9539 only run command buffer once 2021-01-20 17:17:39 -05:00
Dillon Beliveau
23972be4a7 Use ubuntu 20.04 for build pipeline 2021-01-19 23:36:02 -05:00
Dillon Beliveau
d89fe8d29f add vulkan headers include path to imgui module 2021-01-19 23:05:57 -05:00
Dillon Beliveau
3e481f3c2b UI tweaks 2021-01-19 23:05:50 -05:00
Dillon Beliveau
395c842c58 swapping between roms deals with different backup files correctly 2021-01-19 22:12:08 -05:00
Dillon Beliveau
f687ac01b6 file browser, and allow swapping out ROM 2021-01-19 21:53:45 -05:00
Dillon Beliveau
58cb143f83 Display UI on a blank screen when no ROM loaded 2021-01-19 21:09:22 -05:00
Dillon Beliveau
6c51fca0b4 imgui metrics with ImPlot 2021-01-19 00:06:31 -05:00
Dillon Beliveau
b138a4de8b start working on UI 2021-01-18 21:34:21 -05:00
Dillon Beliveau
9d002efc9f finally got imgui working 2021-01-18 21:10:54 -05:00
Dillon Beliveau
1c9bb1a54c missed some zeroes 2021-01-18 14:08:44 -05:00
Dillon Beliveau
dd8eb8d918 use memcpy for HLEing the pif rom's DMA 2021-01-17 17:08:24 -05:00
Dillon Beliveau
bf03a6219e buggy round instructions 2021-01-17 16:47:24 -05:00
Dillon Beliveau
1901617402 these were wrong, so mark them as unimplemented again 2021-01-17 16:25:51 -05:00
Dillon Beliveau
fde580b70c stub cp1 round instructions 2021-01-17 16:21:40 -05:00
Dillon Beliveau
78077e7e55 exception updates & implement TRAP exception 2021-01-17 15:35:35 -05:00
Dillon Beliveau
0d28224371 do work in rax 2021-01-17 15:06:25 -05:00
Dillon Beliveau
6bdaef1bc6 these don't sign extend 2021-01-17 14:21:13 -05:00
Dillon Beliveau
ed3b92c014 dsrl32, dsra32 2021-01-17 14:03:01 -05:00
Dillon Beliveau
e4747d501d fix doubleword shifts, add dsll32 2021-01-17 14:01:46 -05:00
Dillon Beliveau
351b26f04f more fast versions of instructions 2021-01-17 13:48:51 -05:00
Dillon Beliveau
5a0b1f551b Merge branch 'register-allocation' 2021-01-17 12:44:01 -05:00
Dillon Beliveau
dfebb66bc1 variable shifts, use al in slti(u) 2021-01-17 12:34:25 -05:00
Dillon Beliveau
310d3669fb upgrade dynasm, don't use rcx for register allocation 2021-01-17 12:25:04 -05:00