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Author SHA1 Message Date
Dillon Beliveau
5ab318ae72 macroin' and fixin' - (d)addi(u) shouldn't write to r0 2020-12-20 16:06:35 -05:00
Dillon Beliveau
b75d08ac59 fix addi/addiu 2020-12-20 15:52:23 -05:00
Dillon Beliveau
a675c11fd0 test_rom uses dynarec 2020-12-20 15:52:10 -05:00
Dillon Beliveau
f0c19ba275 addi/addiu don't use handlers at all 2020-12-20 14:43:09 -05:00
Dillon Beliveau
df4364c000 always bounds-check ROM 2020-12-17 23:43:41 -05:00
Dillon Beliveau
8eae9a3dda Function for releasing RSP semaphore 2020-12-17 23:42:58 -05:00
Dillon Beliveau
040bb6f0c6 Revert "don't queue samples if we already have a full second of audio available" 
This reverts commit eb6c41a592.
 2020-12-13 17:45:16 -05:00
Dillon Beliveau
0d9d680cbb latest version of parallel-rdp 2020-12-13 15:03:48 -05:00
Dillon Beliveau
8df492a53a load pif rom if it exists 2020-12-13 15:03:41 -05:00
Dillon Beliveau
fdd544e75b commented out definitions 2020-12-13 14:35:50 -05:00
Dillon Beliveau
55454cbad4 use MAIN_DEPENDENCY 2020-12-13 14:35:41 -05:00
Dillon Beliveau
3861a8e884 CMake updates to work with Ninja generator 2020-12-13 14:03:01 -05:00
Dillon Beliveau
20e3bb388b better name 2020-12-13 13:50:35 -05:00
Dillon Beliveau
eb6c41a592 don't queue samples if we already have a full second of audio available 2020-12-13 13:49:51 -05:00
Dillon Beliveau
a20ad247ba all macro compiles together 2020-12-13 13:23:10 -05:00
Dillon Beliveau
78ac1f50c8 better variable name to not confuse myself 2020-12-13 02:01:45 -05:00
Dillon Beliveau
cc87506698 reset cpu steps to zero to not run too many RSP steps when it's enabled after being disabled for a while 2020-12-13 01:40:08 -05:00
Dillon Beliveau
7509cb5410 timing tweaks in logtester 2020-12-13 01:38:16 -05:00
Dillon Beliveau
7f9abd4e9d when CP1 disabled, don't execute the instruction at all 2020-12-13 01:36:53 -05:00
Dillon Beliveau
0c64e52422 eax and notes 2020-12-13 01:36:08 -05:00
Dillon Beliveau
a56a9594e5 use correct name 2020-12-13 01:35:58 -05:00
Dillon Beliveau
3f05940cbf logtester updates to read jit sync logs 2020-12-12 23:52:36 -05:00
Dillon Beliveau
6db8562720 space 2020-12-12 23:52:02 -05:00
Dillon Beliveau
b9c440659f optionally log jit sync points 2020-12-12 22:42:44 -05:00
Dillon Beliveau
73bca68855 more macros to cut down on LOC 2020-12-12 21:54:51 -05:00
Dillon Beliveau
bbaff5596a cut down on a bit of code duplication with some macro use 2020-12-12 21:36:31 -05:00
Dillon Beliveau
6ea375b210 fix logging compilations 2020-12-12 21:18:48 -05:00
Dillon Beliveau
a6dade9566 LFV and SFV with bug warnings 2020-12-12 18:55:03 -05:00
Dillon Beliveau
060f46e4be quiet down these logs 2020-12-12 18:47:18 -05:00
Dillon Beliveau
88a29fba2b interpreter only: dmult, dsra, bltzal 2020-12-12 18:47:05 -05:00
Dillon Beliveau
3431c24ec5 DSRLV 2020-12-12 14:59:27 -05:00
Dillon Beliveau
45dfb97456 add correct amount to length 2020-12-12 14:57:17 -05:00
Dillon Beliveau
71c50af370 use same new timing code in the interpreter as the jit 2020-12-08 01:58:30 -05:00
Dillon Beliveau
771a609f6c abs.s and abs.d 2020-12-08 01:46:19 -05:00
Dillon Beliveau
5bef1fb883 RSP features and stubbing to make OoT happy 2020-12-08 01:33:07 -05:00
Dillon Beliveau
0d6352f5ef 4x upscaling by default 2020-12-08 01:09:20 -05:00
Dillon Beliveau
0ec6003d02 fix tests 2020-12-08 01:09:05 -05:00
Dillon Beliveau
4db1d5faff don't need to check when FR changes 2020-12-08 00:59:48 -05:00
Dillon Beliveau
dcc89660c0 register access functions to own header 2020-12-08 00:59:07 -05:00
Dillon Beliveau
f09b7a3c04 checks for 64 bit addressing enabled and leaving kernel mode 2020-12-08 00:34:24 -05:00
Dillon Beliveau
7b5b267206 sign-extend linked PC 2020-12-08 00:33:28 -05:00
Dillon Beliveau
be12de010f correct initial value of CP0 status 2020-12-08 00:06:58 -05:00
Dillon Beliveau
4a06c3b594 correctly handle FPU register accesses 2020-12-07 23:17:04 -05:00
Dillon Beliveau
f08237518a commented out vulkan debug definition 2020-12-07 22:56:15 -05:00
Dillon Beliveau
25e269c722 new structure for holding FPRs 2020-12-07 22:55:11 -05:00
Dillon Beliveau
58bd80fc28 begin reworking FPU access functions 2020-12-07 22:47:00 -05:00
Dillon Beliveau
5c346cb746 DMTC1/DMFC1 2020-12-07 21:20:08 -05:00
Dillon Beliveau
356f6e97ad compile a new block from inside the handler 2020-12-06 11:51:23 -05:00
Dillon Beliveau
3f37439c53 latest version of parallel-rdp 2020-12-06 02:15:08 -05:00
Dillon Beliveau
cf46ada719 fix vulkan validation errors by ensuring images have the correct properties 2020-12-06 01:57:57 -05:00