mirror of
https://github.com/n64dev/cen64.git
synced 2025-04-02 10:31:54 -04:00
335611d617
izy noticed that the branch LUT was generating memory moves and could be replaced with an inlined function that coerces gcc into generating a lea in its place: 4005ac: 8d 1c 00 lea (%rax,%rax,1),%ebx 4005af: c1 fb 1f sar $0x1f,%ebx 4005b2: f7 d3 not %ebx (no memory access) 4005b9: c1 e8 1e shr $0x1e,%eax 4005bc: 83 e0 01 and $0x1,%eax 4005bf: 44 8b 24 85 90 07 40 mov 0x400790(,%rax,4),%r12d (original has memory access) This ends up optimizing branch instructions quite nicely: "You see that when you use "mask" you execute "~mask". The compiler understands that ~(~(partial_mask)) = partial_mask and removes both "NOTs". So in this case my version uses 2 instructions and no memory access/cache pollution."
585 lines
15 KiB
C
585 lines
15 KiB
C
//
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// rsp/functions.c: RSP execution functions.
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//
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// CEN64: Cycle-Accurate Nintendo 64 Emulator.
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// Copyright (C) 2015, Tyler J. Stachecki.
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//
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// This file is subject to the terms and conditions defined in
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// 'LICENSE', which is part of this source code package.
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//
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#define RSP_BUILD_OP(op, func, flags) \
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(RSP_##func)
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#include "common.h"
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#include "bus/controller.h"
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#include "rsp/cp0.h"
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#include "rsp/cpu.h"
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#include "rsp/decoder.h"
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#include "rsp/opcodes.h"
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#include "rsp/opcodes_priv.h"
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#include "rsp/pipeline.h"
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#include "vr4300/interface.h"
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// Mask to negate second operand if subtract operation.
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cen64_align(static const uint32_t rsp_addsub_lut[4], 16) = {
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0x0U, ~0x0U, ~0x0U, ~0x0U
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};
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// Mask to select outputs for bitwise operations.
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cen64_align(static const uint32_t rsp_bitwise_lut[4][2], 32) = {
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{~0U, 0U}, // AND
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{~0U, ~0U}, // OR
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{ 0U, ~0U}, // XOR
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{ 0U, 0U}, // -
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};
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// Mask to denote which part of the vector to load/store.
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cen64_align(static const uint16_t rsp_bdls_lut[4][4], CACHE_LINE_SIZE) = {
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{0xFF00, 0x0000, 0x0000, 0x0000}, // B
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{0xFFFF, 0x0000, 0x0000, 0x0000}, // S
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{0xFFFF, 0xFFFF, 0x0000, 0x0000}, // L
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{0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF}, // D
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};
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cen64_align(static const uint16_t rsp_qr_lut[16][8], CACHE_LINE_SIZE) = {
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{0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF},
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{0x00FF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF},
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{0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF},
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{0x0000, 0x00FF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF},
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{0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF},
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{0x0000, 0x0000, 0x00FF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF},
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{0x0000, 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF},
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{0x0000, 0x0000, 0x0000, 0x00FF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF},
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{0x0000, 0x0000, 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF},
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{0x0000, 0x0000, 0x0000, 0x0000, 0x00FF, 0xFFFF, 0xFFFF, 0xFFFF},
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{0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF},
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{0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00FF, 0xFFFF, 0xFFFF},
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{0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xFFFF, 0xFFFF},
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{0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00FF, 0xFFFF},
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{0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xFFFF},
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{0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00FF},
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};
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// Mask to select link address register for some branches.
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static inline uint32_t rsp_branch_mask(uint32_t iw, unsigned index) {
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iw = (uint32_t)( (int32_t)(iw << (31 - index)) >> 31 );
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return ~iw; /* ones' complement must be done last on return */
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}
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// Mask to selectively sign-extend loaded values.
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cen64_align(static const uint32_t rsp_load_sex_mask[8], 32) = {
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~0U, ~0U, 0U, ~0U, // sex
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0xFFU, 0xFFFFU, 0U, ~0U, // zex
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};
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// Function to sign-extend 6-bit values.
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static inline unsigned sign_extend_6(int i) {
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return (i << (32 - 7)) >> (32 - 7);
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}
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//
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// ADDIU
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// LUI
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// SUBIU
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//
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void RSP_ADDIU_LUI_SUBIU(struct rsp *rsp,
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uint32_t iw, uint32_t rs, uint32_t rt) {
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struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
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unsigned immshift = iw >> 24 & 0x10;
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unsigned dest;
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dest = GET_RT(iw);
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rt = (int16_t) iw;
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rt = rs + (rt << immshift);
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exdf_latch->result.result = rt;
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exdf_latch->result.dest = dest;
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}
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//
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// ADDU
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// SUBU
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//
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void RSP_ADDU_SUBU(struct rsp *rsp,
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uint32_t iw, uint32_t rs, uint32_t rt) {
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struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
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uint32_t mask = rsp_addsub_lut[iw & 0x2];
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unsigned dest;
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uint32_t rd;
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dest = GET_RD(iw);
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rt = (rt ^ mask) - mask;
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rd = rs + rt;
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exdf_latch->result.result = rd;
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exdf_latch->result.dest = dest;
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}
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//
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// AND
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// OR
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// XOR
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//
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void RSP_AND_OR_XOR(struct rsp *rsp,
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uint32_t iw, uint32_t rs, uint32_t rt) {
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struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
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uint32_t and_mask = rsp_bitwise_lut[iw & 0x3][0];
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uint32_t xor_mask = rsp_bitwise_lut[iw & 0x3][1];
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unsigned dest;
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uint32_t rd;
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dest = GET_RD(iw);
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rd = ((rs & rt) & and_mask) | ((rs ^ rt) & xor_mask);
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exdf_latch->result.result = rd;
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exdf_latch->result.dest = dest;
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}
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//
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// ANDI
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// ORI
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// XORI
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//
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void RSP_ANDI_ORI_XORI(struct rsp *rsp,
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uint32_t iw, uint32_t rs, uint32_t rt) {
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struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
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uint32_t and_mask = rsp_bitwise_lut[iw >> 26 & 0x3][0];
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uint32_t xor_mask = rsp_bitwise_lut[iw >> 26 & 0x3][1];
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unsigned dest;
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dest = GET_RT(iw);
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rt = (uint16_t) iw;
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rt = ((rs & rt) & and_mask) | ((rs ^ rt) & xor_mask);
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exdf_latch->result.result = rt;
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exdf_latch->result.dest = dest;
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}
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//
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// BEQ
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// BNE
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//
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// TODO: Adjust branch target for RSP IMEM range.
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//
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void RSP_BEQ_BNE(struct rsp *rsp,
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uint32_t iw, uint32_t rs, uint32_t rt) {
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struct rsp_ifrd_latch *ifrd_latch = &rsp->pipeline.ifrd_latch;
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struct rsp_rdex_latch *rdex_latch = &rsp->pipeline.rdex_latch;
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uint32_t offset = (uint32_t) ((int16_t) iw) << 2;
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bool is_ne = iw >> 26 & 0x1;
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bool cmp = rs == rt;
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if (cmp == is_ne)
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return;
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ifrd_latch->pc = (rdex_latch->common.pc + offset + 4) & 0xFFC;
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}
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//
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// BGEZ
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// BLTZ
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//
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// TODO: Adjust branch target for RSP IMEM range.
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//
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void RSP_BGEZ_BLTZ(
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struct rsp *rsp,
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uint32_t iw, uint32_t rs, uint32_t unused(rt)) {
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struct rsp_ifrd_latch *ifrd_latch = &rsp->pipeline.ifrd_latch;
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struct rsp_rdex_latch *rdex_latch = &rsp->pipeline.rdex_latch;
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uint32_t offset = (uint32_t) ((int16_t) iw) << 2;
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bool is_ge = iw >> 16 & 0x1;
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bool cmp = (int32_t) rs < 0;
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if (cmp == is_ge)
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return;
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ifrd_latch->pc = (rdex_latch->common.pc + offset + 4) & 0xFFC;
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}
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//
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// BGEZAL
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// BLTZAL
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//
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// TODO: Adjust branch target for RSP IMEM range.
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//
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void RSP_BGEZAL_BLTZAL(
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struct rsp *rsp, uint32_t iw, uint32_t rs, uint32_t unused(rt)) {
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struct rsp_ifrd_latch *ifrd_latch = &rsp->pipeline.ifrd_latch;
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struct rsp_rdex_latch *rdex_latch = &rsp->pipeline.rdex_latch;
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struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
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uint32_t offset = (uint32_t) ((int16_t) iw) << 2;
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bool is_ge = iw >> 16 & 0x1;
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bool cmp = (int32_t) rs < 0;
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exdf_latch->result.result = 0x1000 | (rdex_latch->common.pc + 8);
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exdf_latch->result.dest = RSP_REGISTER_RA;
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if (cmp == is_ge)
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return;
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ifrd_latch->pc = (rdex_latch->common.pc + offset + 4) & 0xFFC;
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}
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//
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// BGTZ
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// BLEZ
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//
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// TODO: Adjust branch target for RSP IMEM range.
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//
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void RSP_BGTZ_BLEZ(
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struct rsp *rsp, uint32_t iw, uint32_t rs, uint32_t unused(rt)) {
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struct rsp_ifrd_latch *ifrd_latch = &rsp->pipeline.ifrd_latch;
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struct rsp_rdex_latch *rdex_latch = &rsp->pipeline.rdex_latch;
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uint32_t offset = (uint32_t) ((int16_t) iw) << 2;
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bool is_gt = iw >> 26 & 0x1;
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bool cmp = (int32_t) rs <= 0;
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if (cmp == is_gt)
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return;
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ifrd_latch->pc = (rdex_latch->common.pc + offset + 4) & 0xFFC;
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}
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//
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// BREAK
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//
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void RSP_BREAK(struct rsp *rsp,
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uint32_t iw, uint32_t rs, uint32_t rt) {
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struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
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uint32_t result = rsp->regs[RSP_CP0_REGISTER_SP_STATUS] |
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(SP_STATUS_HALT | SP_STATUS_BROKE);
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if (rsp->regs[RSP_CP0_REGISTER_SP_STATUS] & SP_STATUS_INTR_BREAK)
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signal_rcp_interrupt(rsp->bus->vr4300, MI_INTR_SP);
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exdf_latch->result.dest = RSP_CP0_REGISTER_SP_STATUS;
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exdf_latch->result.result = result;
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}
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//
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// LB
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// LBU
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// LH
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// LHU
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// LW
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// SB
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// SH
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// SW
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//
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cen64_hot void RSP_INT_MEM(struct rsp *rsp,
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uint32_t iw, uint32_t rs, uint32_t rt) {
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struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
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uint32_t address = rs + (int16_t) iw;
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uint32_t sel_mask = (int32_t) (iw << 2) >> 31;
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unsigned request_index = (iw >> 26 & 0x7);
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uint32_t rdqm = rsp_load_sex_mask[request_index];
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unsigned request_size = request_index & 0x3;
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unsigned lshiftamt = (3 - request_size) << 3;
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uint32_t wdqm = ~0U << lshiftamt;
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exdf_latch->request.addr = address;
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exdf_latch->request.packet.p_int.data = rt << lshiftamt;
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exdf_latch->request.packet.p_int.rdqm = rdqm;
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exdf_latch->request.type = RSP_MEM_REQUEST_INT_MEM;
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exdf_latch->request.packet.p_int.rshift = lshiftamt;
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exdf_latch->request.packet.p_int.wdqm = sel_mask & wdqm;
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exdf_latch->result.dest = ~sel_mask & GET_RT(iw);
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}
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//
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// INVALID
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//
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void RSP_INVALID(struct rsp *rsp,
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uint32_t iw, uint32_t unused(rs), uint32_t unused(rt)) {
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#ifndef NDEBUG
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struct rsp_rdex_latch *rdex_latch = &rsp->pipeline.rdex_latch;
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debug("Unimplemented instruction: %s [0x%.8X] @ 0x%.8X\n",
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rsp_opcode_mnemonics[rdex_latch->opcode.id],
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iw, rdex_latch->common.pc);
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#endif
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}
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//
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// J
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// JAL
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//
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void RSP_J_JAL(struct rsp *rsp,
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uint32_t iw, uint32_t rs, uint32_t rt) {
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struct rsp_ifrd_latch *ifrd_latch = &rsp->pipeline.ifrd_latch;
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struct rsp_rdex_latch *rdex_latch = &rsp->pipeline.rdex_latch;
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struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
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uint32_t target = iw << 2 & 0xFFC;
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uint32_t mask = rsp_branch_mask(iw, 26); //is_jal
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exdf_latch->result.result = 0x1000 | ((rdex_latch->common.pc + 8) & 0xFFC);
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exdf_latch->result.dest = RSP_REGISTER_RA & ~mask;
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ifrd_latch->pc = target;
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}
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//
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// JALR
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// JR
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//
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void RSP_JALR_JR(struct rsp *rsp,
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uint32_t iw, uint32_t rs, uint32_t unused(rt)) {
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struct rsp_ifrd_latch *ifrd_latch = &rsp->pipeline.ifrd_latch;
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struct rsp_rdex_latch *rdex_latch = &rsp->pipeline.rdex_latch;
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struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
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uint32_t mask = rsp_branch_mask(iw, 0); // is_jalr
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unsigned rd = GET_RD(iw);
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exdf_latch->result.result = 0x1000 | ((rdex_latch->common.pc + 8) & 0xFFC);
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exdf_latch->result.dest = rd & ~mask;
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ifrd_latch->pc = rs & 0xFFC;
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}
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//
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// LBV
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// LDV
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// LLV
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// LSV
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// SBV
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// SDV
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// SLV
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// SSV
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//
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void RSP_LBDLSV_SBDLSV(struct rsp *rsp,
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uint32_t iw, uint32_t rs, uint32_t rt) {
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struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
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unsigned shift_and_idx = iw >> 11 & 0x3;
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unsigned dest = GET_VT(iw);
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exdf_latch->request.addr = rs + (sign_extend_6(iw) << shift_and_idx);
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__m128i vdqm = _mm_loadl_epi64((__m128i *) (rsp_bdls_lut[shift_and_idx]));
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_mm_store_si128((__m128i *) exdf_latch->request.packet.p_vect.vdqm.e, vdqm);
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exdf_latch->request.packet.p_vect.element = GET_EL(iw);
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exdf_latch->request.type = RSP_MEM_REQUEST_VECTOR;
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exdf_latch->request.packet.p_vect.vldst_func = (iw >> 29 & 0x1)
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? rsp_vstore_group1
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: rsp_vload_group1;
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exdf_latch->request.packet.p_vect.dest = dest;
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}
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//
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// LPV
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// LUV
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// SPV
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// SUV
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//
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void RSP_LFHPUV_SFHPUV(struct rsp *rsp,
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uint32_t iw, uint32_t rs, uint32_t rt) {
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struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
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unsigned dest = GET_VT(iw);
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static const enum rsp_mem_request_type fhpu_type_lut[4] = {
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RSP_MEM_REQUEST_PACK,
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RSP_MEM_REQUEST_UPACK,
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RSP_MEM_REQUEST_HALF,
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RSP_MEM_REQUEST_FOURTH
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};
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exdf_latch->request.addr = rs + (sign_extend_6(iw) << 3);
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// memcpy(&exdf_latch->request.vdqm.e,
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// rsp_fhpu_lut[exdf_latch->request.addr & 0xF],
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// sizeof(exdf_latch->request.vdqm.e));
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exdf_latch->request.type = fhpu_type_lut[(iw >> 11 & 0x1F) - 6];
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exdf_latch->request.packet.p_vect.vldst_func = (iw >> 29 & 0x1)
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? rsp_vstore_group2
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: rsp_vload_group2;
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exdf_latch->request.packet.p_vect.dest = dest;
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}
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//
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// LQV
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// LRV
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// SQV
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// SRV
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//
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void RSP_LQRV_SQRV(struct rsp *rsp,
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uint32_t iw, uint32_t rs, uint32_t rt) {
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struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
|
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unsigned dest = GET_VT(iw);
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|
|
|
exdf_latch->request.addr = rs + (sign_extend_6(iw) << 4);
|
|
|
|
memcpy(exdf_latch->request.packet.p_vect.vdqm.e,
|
|
rsp_qr_lut[exdf_latch->request.addr & 0xF],
|
|
sizeof(exdf_latch->request.packet.p_vect.vdqm.e));
|
|
|
|
exdf_latch->request.packet.p_vect.element = GET_EL(iw);
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|
exdf_latch->request.type = (iw >> 11 & 0x1)
|
|
? RSP_MEM_REQUEST_REST
|
|
: RSP_MEM_REQUEST_QUAD;
|
|
|
|
exdf_latch->request.packet.p_vect.vldst_func = (iw >> 29 & 0x1)
|
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? rsp_vstore_group4
|
|
: rsp_vload_group4;
|
|
|
|
exdf_latch->request.packet.p_vect.dest = dest;
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|
}
|
|
|
|
//
|
|
// NOR
|
|
//
|
|
void RSP_NOR(struct rsp *rsp,
|
|
uint32_t iw, uint32_t rs, uint32_t rt) {
|
|
struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
|
|
unsigned dest = GET_RD(iw);
|
|
|
|
exdf_latch->result.result = ~(rs | rt);
|
|
exdf_latch->result.dest = dest;
|
|
}
|
|
|
|
//
|
|
// SLL
|
|
// SLLV
|
|
//
|
|
void RSP_SLL_SLLV(struct rsp *rsp,
|
|
uint32_t iw, uint32_t rs, uint32_t rt) {
|
|
struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
|
|
|
|
unsigned dest = GET_RD(iw);
|
|
unsigned sa = (rs & 0x1F) + (iw >> 6 & 0x1F);
|
|
|
|
exdf_latch->result.result = rt << sa;
|
|
exdf_latch->result.dest = dest;
|
|
}
|
|
|
|
//
|
|
// SLT
|
|
//
|
|
void RSP_SLT(struct rsp *rsp,
|
|
uint32_t iw, uint32_t rs, uint32_t rt) {
|
|
struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
|
|
unsigned dest = GET_RD(iw);
|
|
|
|
exdf_latch->result.result = (int32_t) rs < (int32_t) rt;
|
|
exdf_latch->result.dest = dest;
|
|
}
|
|
|
|
//
|
|
// SLTI
|
|
//
|
|
void RSP_SLTI(struct rsp *rsp,
|
|
uint32_t iw, uint32_t rs, uint32_t rt) {
|
|
struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
|
|
|
|
unsigned dest = GET_RT(iw);
|
|
int32_t imm = (int16_t) iw;
|
|
|
|
exdf_latch->result.result = (int32_t) rs < imm;
|
|
exdf_latch->result.dest = dest;
|
|
}
|
|
|
|
//
|
|
// SLTIU
|
|
//
|
|
void RSP_SLTIU(struct rsp *rsp,
|
|
uint32_t iw, uint32_t rs, uint32_t rt) {
|
|
struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
|
|
|
|
unsigned dest = GET_RT(iw);
|
|
uint32_t imm = (int16_t) iw;
|
|
|
|
exdf_latch->result.result = rs < imm;
|
|
exdf_latch->result.dest = dest;
|
|
}
|
|
|
|
//
|
|
// SLTU
|
|
//
|
|
void RSP_SLTU(struct rsp *rsp,
|
|
uint32_t iw, uint32_t rs, uint32_t rt) {
|
|
struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
|
|
unsigned dest = GET_RD(iw);
|
|
|
|
exdf_latch->result.result = rs < rt;
|
|
exdf_latch->result.dest = dest;
|
|
}
|
|
|
|
//
|
|
// SRA
|
|
//
|
|
void RSP_SRA(struct rsp *rsp,
|
|
uint32_t iw, uint32_t unused(rs), uint32_t rt) {
|
|
struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
|
|
unsigned dest = GET_RD(iw);
|
|
unsigned sa = iw >> 6 & 0x1F;
|
|
|
|
exdf_latch->result.result = (int32_t) rt >> sa;
|
|
exdf_latch->result.dest = dest;
|
|
}
|
|
|
|
//
|
|
// SRAV
|
|
//
|
|
void RSP_SRAV(struct rsp *rsp,
|
|
uint32_t iw, uint32_t rs, uint32_t rt) {
|
|
struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
|
|
unsigned dest = GET_RD(iw);
|
|
unsigned sa = rs & 0x1F;
|
|
|
|
exdf_latch->result.result = (int32_t) rt >> sa;
|
|
exdf_latch->result.dest = dest;
|
|
}
|
|
|
|
//
|
|
// SRL
|
|
//
|
|
void RSP_SRL(struct rsp *rsp,
|
|
uint32_t iw, uint32_t unused(rs), uint32_t rt) {
|
|
struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
|
|
unsigned dest = GET_RD(iw);
|
|
unsigned sa = iw >> 6 & 0x1F;
|
|
|
|
exdf_latch->result.result = rt >> sa;
|
|
exdf_latch->result.dest = dest;
|
|
}
|
|
|
|
//
|
|
// SRLV
|
|
//
|
|
void RSP_SRLV(struct rsp *rsp,
|
|
uint32_t iw, uint32_t rs, uint32_t rt) {
|
|
struct rsp_exdf_latch *exdf_latch = &rsp->pipeline.exdf_latch;
|
|
unsigned dest = GET_RD(iw);
|
|
unsigned sa = rs & 0x1F;
|
|
|
|
exdf_latch->result.result = rt >> sa;
|
|
exdf_latch->result.dest = dest;
|
|
}
|
|
|
|
// Function lookup table.
|
|
cen64_align(const rsp_function
|
|
rsp_function_table[NUM_RSP_OPCODES], CACHE_LINE_SIZE) = {
|
|
#define X(op) op,
|
|
#include "rsp/opcodes.md"
|
|
#undef X
|
|
};
|
|
|