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131 lines
3.8 KiB
C
131 lines
3.8 KiB
C
//
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// bus/controller.c: System bus controller.
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//
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// CEN64: Cycle-Accurate Nintendo 64 Emulator.
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// Copyright (C) 2015, Tyler J. Stachecki.
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//
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// This file is subject to the terms and conditions defined in
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// 'LICENSE', which is part of this source code package.
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//
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#include "common.h"
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#include "ai/controller.h"
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#include "bus/address.h"
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#include "bus/controller.h"
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#include "bus/memorymap.h"
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#include "dd/controller.h"
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#include "pi/controller.h"
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#include "ri/controller.h"
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#include "si/controller.h"
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#include "rdp/cpu.h"
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#include "rdp/interface.h"
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#include "rsp/cpu.h"
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#include "rsp/interface.h"
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#include "vi/controller.h"
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#include "vr4300/cpu.h"
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#include "vr4300/interface.h"
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#define NUM_MAPPINGS 16
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struct bus_controller_mapping {
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memory_rd_function read;
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memory_wr_function write;
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uint32_t address;
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uint32_t length;
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};
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// Initializes the bus component.
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int bus_init(struct bus_controller *bus) {
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unsigned i;
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static const struct bus_controller_mapping mappings[NUM_MAPPINGS] = {
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{read_ai_regs, write_ai_regs, AI_REGS_BASE_ADDRESS, AI_REGS_ADDRESS_LEN},
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{read_dp_regs, write_dp_regs, DP_REGS_BASE_ADDRESS, DP_REGS_ADDRESS_LEN},
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{read_mi_regs, write_mi_regs, MI_REGS_BASE_ADDRESS, MI_REGS_ADDRESS_LEN},
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{read_pi_regs, write_pi_regs, PI_REGS_BASE_ADDRESS, PI_REGS_ADDRESS_LEN},
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{read_ri_regs, write_ri_regs, RI_REGS_BASE_ADDRESS, RI_REGS_ADDRESS_LEN},
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{read_si_regs, write_si_regs, SI_REGS_BASE_ADDRESS, SI_REGS_ADDRESS_LEN},
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{read_sp_regs, write_sp_regs, SP_REGS_BASE_ADDRESS, SP_REGS_ADDRESS_LEN},
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{read_vi_regs, write_vi_regs, VI_REGS_BASE_ADDRESS, VI_REGS_ADDRESS_LEN},
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{read_cart_rom, write_cart_rom, ROM_CART_BASE_ADDRESS, ROM_CART_ADDRESS_LEN},
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{read_flashram, write_flashram, FLASHRAM_BASE_ADDRESS, FLASHRAM_ADDRESS_LEN},
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{read_dd_controller, write_dd_controller, DD_CONTROLLER_ADDRESS, DD_CONTROLLER_LEN},
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{read_dd_ipl_rom, write_dd_ipl_rom, DD_IPL_ROM_ADDRESS, DD_IPL_ROM_LEN},
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{read_pif_rom_and_ram, write_pif_rom_and_ram, PIF_BASE_ADDRESS, PIF_ADDRESS_LEN},
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{read_rdram_regs, write_rdram_regs, RDRAM_REGS_BASE_ADDRESS, RDRAM_REGS_ADDRESS_LEN},
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{read_sp_regs2, write_sp_regs2, SP_REGS2_BASE_ADDRESS, SP_REGS2_ADDRESS_LEN},
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{read_sp_mem, write_sp_mem, SP_MEM_BASE_ADDRESS, SP_MEM_ADDRESS_LEN},
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};
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void *instances[NUM_MAPPINGS] = {
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bus->ai,
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bus->rdp,
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bus->vr4300,
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bus->pi,
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bus->ri,
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bus->si,
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bus->rsp,
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bus->vi,
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bus->pi,
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bus->pi,
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bus->dd,
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bus->dd,
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bus->si,
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bus->si,
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bus->ri,
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bus->rsp,
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bus->rsp
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};
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create_memory_map(&bus->map);
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for (i = 0; i < NUM_MAPPINGS; i++)
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if (map_address_range(&bus->map, mappings[i].address, mappings[i].length,
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instances[i], mappings[i].read, mappings[i].write))
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return 1;
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return 0;
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}
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// Issues a read request to the bus.
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int bus_read_word(void *component, uint32_t address, uint32_t *word) {
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const struct memory_mapping *node;
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struct bus_controller *bus;
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memcpy(&bus, component, sizeof(bus));
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if (address < RDRAM_BASE_ADDRESS_LEN)
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return read_rdram(bus->ri, address, word);
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else if ((node = resolve_mapped_address(&bus->map, address)) == NULL) {
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debug("bus_read_word: Failed to access: 0x%.8X\n", address);
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*word = 0x00000000U;
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return 0;
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}
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return node->on_read(node->instance, address, word);
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}
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// Issues a write request to the bus.
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int bus_write_word(void *component,
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uint32_t address, uint32_t word, uint32_t dqm) {
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const struct memory_mapping *node;
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struct bus_controller *bus;
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memcpy(&bus, component, sizeof(bus));
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if (address < RDRAM_BASE_ADDRESS_LEN)
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return write_rdram(bus->ri, address, word & dqm, dqm);
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else if ((node = resolve_mapped_address(&bus->map, address)) == NULL) {
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debug("bus_write_word: Failed to access: 0x%.8X\n", address);
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return 0;
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}
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return node->on_write(node->instance, address, word & dqm, dqm);
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}
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