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130 commits

Author SHA1 Message Date
Tyler Stachecki
85a21616cc Micro-optimization: faster li emulation. 
If we think about how the assembler forms 32-bit immediates, it
usually generates a lui and addiu pair. Well, if can craft the
simulation such that lui and addiu are the same indirect target
when branching to execution functions, we can reduce the chance
that we'll mispredict and have a resulting pipeline flush on the
host.

Every cycle counts!
 2014-10-25 12:40:27 -04:00
Tyler Stachecki
e698bfe1d1 Improving accuracy of RSP LWC2/SWC2 operations. 2014-10-25 02:06:30 -04:00
Tyler Stachecki
74327ef79e Compress LQV/SQV into one function. 2014-10-24 23:56:42 -04:00
Tyler Stachecki
ba2ca6f427 Fix more byte-ordering issues. This was hard. 2014-10-24 23:43:24 -04:00
Tyler Stachecki
e63b13605e Various LWC2/SWC2 fixes, add VSAR. 2014-10-24 21:07:25 -04:00
Tyler Stachecki
f395be631e Start adding in support for LWC2/SWC2 ops: LQV/SQV. 2014-10-24 18:31:13 -04:00
Tyler Stachecki
519f59f429 Start implementing some vector operators. 2014-10-22 18:15:44 -04:00
Tyler Stachecki
8ccf4eca32 Add writes to RDP space from RSP CP0. 2014-10-20 13:20:09 -04:00
Tyler Stachecki
62ebbd8c54 Fix a typo (wrong enumeration). 2014-10-20 12:58:50 -04:00
Tyler Stachecki
4c2b49c779 Assist optimizations by changing a macro'd value. 2014-10-20 08:10:32 -04:00
Tyler Stachecki
ab8687e263 Remove an unnecessary pair of RF writes. 
We always write to $0 during bypass logic to make sure that a
forwarded value, regardless of it's desination, never alters the
value of $0. Therefore, writing it to the RF as shown here is not
strictly necessary.
 2014-10-20 07:42:07 -04:00
Tyler Stachecki
69b810cfaa Silence an unused variable warning. 2014-10-18 12:31:28 -04:00
Tyler Stachecki
9dc2a36313 Remove some RSP debugging code and sloppyness. 2014-10-18 12:30:36 -04:00
Tyler Stachecki
749b3906c9 Fix RSP DMEM endian issues and load-use code. 2014-10-18 12:26:03 -04:00
Tyler Stachecki
421b0e0519 Implement some RSP DMEM reads and writes. 2014-10-18 11:34:09 -04:00
Tyler Stachecki
4ff41a0e34 Fix DMA/interrupt issues with the RSP. 2014-10-18 11:34:02 -04:00
Tyler Stachecki
df68d13733 FIx some PC-related bugs in the RSP. 2014-10-18 11:33:56 -04:00
Tyler Stachecki
f5dc940dee Prevent the RSP from hanging the IPL. 2014-10-18 11:33:51 -04:00
Tyler Stachecki
0eea4f213e Start fleshing out the RSP backend. 2014-10-18 11:33:44 -04:00
Tyler Stachecki
b421093700 Start fleshing out the RSP frontend. 2014-10-18 11:33:14 -04:00
Tyler Stachecki
f520f6e9b8 Start fleshing out the RSP pipeline. 2014-10-18 11:33:04 -04:00
Tyler Stachecki
7ac625cec1 Implement RSP DMAs, COP0 registers, etc. 2014-10-18 11:32:51 -04:00
Tyler Stachecki
440c51fef2 Add modified functions for RSP. 2014-10-18 11:32:43 -04:00
Tyler Stachecki
71961f0b00 Implement the RSP decoder. 2014-10-18 11:32:36 -04:00
Tyler Stachecki
b20b138d99 Add the RSP opcode entries. 2014-10-18 11:32:27 -04:00
Tyler Stachecki
e605bcc232 Use similar length fields for MMIO register debug. 2014-04-18 17:17:26 -04:00
Tyler Stachecki
9d2bbdfa9c Implement external SP mem read/write. 2014-04-18 13:41:29 -04:00
Tyler Stachecki
25a6ae8431 Mask bus writes to requested type, etc. 2014-04-18 13:34:23 -04:00
Tyler Stachecki
d114038a2b Add option for debugging MMIO register access. 2014-04-18 12:44:57 -04:00
Tyler Stachecki
4560adf7a7 Populate with interfaces and devices. 2014-04-18 11:24:43 -04:00