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21 commits

Author SHA1 Message Date
Tyler Stachecki
dfe7d59ec9 Implement DCB-type stalls. 2015-07-05 08:15:04 -04:00
Derek "Turtle" Roe
c4afd44ed7 See long description 
Replaced all references to simulation with emulation
Updated copyright year
Updated .gitignore to reduce chances of random files being uploaded to
the repo
Added .gitattributes to normalize all text files, and to ignore binary
files (which includes the logo and the NEC PDF)
 2015-07-03 08:18:16 -04:00
Tyler Stachecki
7168fc5e6f Fix a slew of cache bugs. 2015-01-29 10:07:54 -05:00
Tyler Stachecki
d7427d6b73 VR4300: Cache read/write optimizations. 2015-01-10 14:16:40 -05:00
Tyler Stachecki
da2fd05415 Respect the TLB entry conherency bits. 
If the TLB entry 'C bits' indicate the cache isn't to be
used for that virtual address range... don't use the cache.
 2015-01-04 21:33:29 -05:00
Tyler Stachecki
0d7a42c4ce Move cache functionality to the DC stage. 
This is how the actual processor does it. In addition to
design correctness, we have the added benefit of being able
to support cache instructions whose virtual address lies
in a mapped part of the address space.
 2015-01-04 21:10:12 -05:00
Tyler Stachecki
17954bf0b8 Fix bugs, implement WatchLo/Hi support. 2015-01-04 11:52:11 -05:00
Tyler Stachecki
f66894935b Mark more initialization functions as cold. 2014-11-09 19:11:09 -05:00
Tyler Stachecki
1061cec86b Lots of branch folding in the LD/ST aligner. 2014-10-22 18:11:50 -04:00
Tyler Stachecki
6ef9115668 Fix a bunch of TLB translation bugs. 2014-08-23 22:10:46 -04:00
Tyler Stachecki
81c799576a Fill and flush data cache lines as required. 2014-08-21 21:43:07 -04:00
Tyler Stachecki
3ef365b78f Move data memory writes to fault handlers. 2014-08-21 21:42:48 -04:00
Tyler Stachecki
9bd494b4e0 Make busy wait special casing safer. 2014-07-29 09:47:01 -04:00
Tyler Stachecki
596736f64d Hack in support for LDL/LDR. 2014-07-27 00:59:43 -04:00
Tyler Stachecki
d0662e9874 Remove preshift from memory operations. 2014-07-26 14:54:30 -04:00
Tyler Stachecki
2484f31253 Experimental fixes for LWC1/MTC1. 2014-07-02 01:43:41 -04:00
Tyler Stachecki
bce0070159 VR4300: Add support for LWL, LWR instructions. 2014-04-21 13:55:09 -04:00
Tyler Stachecki
809cbe1eb5 Fix issues with loads, hack LD into the pipeline. 2014-04-18 22:03:00 -04:00
Tyler Stachecki
25a6ae8431 Mask bus writes to requested type, etc. 2014-04-18 13:34:23 -04:00
Tyler Stachecki
ca81cc95f5 Start executing PIF ROM. 2014-03-09 22:38:47 -04:00
Tyler Stachecki
2f3aded155 Initial commit. 2014-03-08 11:12:15 -05:00