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43 commits

Author SHA1 Message Date
Derek "Turtle" Roe
c4afd44ed7 See long description 
Replaced all references to simulation with emulation
Updated copyright year
Updated .gitignore to reduce chances of random files being uploaded to
the repo
Added .gitattributes to normalize all text files, and to ignore binary
files (which includes the logo and the NEC PDF)
 2015-07-03 08:18:16 -04:00
Tyler Stachecki
4e8fb2329b Perform some really clever branch folding. 
Fold all the integer loads and stores into one code path.
 2015-01-06 02:14:40 -05:00
Tyler Stachecki
84d19566b9 Merge more functions together. 2015-01-02 23:51:20 -05:00
Tyler Stachecki
7262516636 Start merging RSP vector functions. 
No need to separate all these functions when they contain so
much common code, so start combining things for the sake of
locality and predictor effectiveness (and size). In addition
to these benefits, the CPU backend is usually busy during the
execution of these functions, so suffering a misprediction
isn't as painful (especially seeing as we can potentially
improve the prediction from the indirect branch).
 2015-01-02 22:17:41 -05:00
Tyler Stachecki
03663a68f6 Add an implementation for VMACU. 2015-01-02 20:52:39 -05:00
Tyler Stachecki
7a6ecabcc1 Fix a series of RSP bugs that krom pointed out. 2015-01-01 21:09:08 -05:00
Tyler Stachecki
6a709a4125 Get the Windows build in running condition. 2015-01-01 12:37:26 -05:00
Tyler Stachecki
fea458e70c Add (partial) implementations for LPV/LUV/SPV/SUV. 
Also, cleanup other SSSE3+ accelerated loads and stores.
 2014-12-26 14:19:45 -05:00
Tyler Stachecki
03f04c1b82 Add implementation for MTC2. 2014-12-26 14:19:45 -05:00
Tyler Stachecki
b33f2800ae Add implementation for MFC2. 2014-12-26 14:19:45 -05:00
Tyler Stachecki
6faca60054 Start reworking RSP vector loads and stores. 2014-12-26 14:19:45 -05:00
Tyler Stachecki
f1929a056c Commit AIO's VMACF implementation. 2014-12-24 15:18:59 -05:00
Tyler Stachecki
ab8dde80e9 Add AIO's implementation for VMULU. 2014-12-23 01:10:15 -05:00
Tyler Stachecki
e52e031ce3 Add implementations for VRSQ, VRSQL, and VRSQH. 2014-12-22 20:47:48 -05:00
Tyler Stachecki
4b6904240e Add implementations for VRCP, VRCPL, and VRCPH. 2014-12-22 20:29:16 -05:00
Tyler Stachecki
73709f4c45 Add implementation for VCR. 2014-12-22 13:01:03 -05:00
Tyler Stachecki
88310a8104 Add AIO's implementation for VMULF. 2014-12-22 09:50:29 -05:00
Tyler Stachecki
f268795da5 Add implementation for VMRG. 2014-12-21 15:49:44 -05:00
Tyler Stachecki
9f4664a4b6 Add implementation for VADDC. 2014-12-21 15:29:16 -05:00
Tyler Stachecki
a955bf1e2c Add implementation for VSUBC. 2014-12-21 15:07:00 -05:00
Tyler Stachecki
f199c7bac8 Add implementation for VABS. 2014-12-21 12:59:36 -05:00
Tyler Stachecki
0be40f4358 Add implementations for VGE and VLT. 2014-12-21 11:08:00 -05:00
Tyler Stachecki
dc50279609 Add implementations for VEQ and VNE. 2014-12-21 10:39:10 -05:00
Tyler Stachecki
e1de6cd92d Add implementations for VCH. 2014-12-21 09:29:58 -05:00
Tyler Stachecki
145141225e Add implementations for VCL and CFC2. 2014-12-20 12:27:38 -05:00
Tyler Stachecki
9f8a9f9d62 Add implementations of VMADH and VMUDH. 2014-11-08 14:01:41 -05:00
Tyler Stachecki
007d72eda1 Add implementations of VMADL and VMADM. 2014-11-08 12:21:06 -05:00
Tyler Stachecki
e89f054674 Optimize extremely aggressively. 
Tell GCC to optimize cold functions for size and stash them away in
a separate part of the binary. Put the simulate core, meanwhile, on
the hot path. Also, bump optimization to -O3 as we can now "afford"
to do so.
 2014-11-05 08:39:47 -05:00
Tyler Stachecki
b668296589 Add implementations of VADD and VSUB. 2014-11-03 18:06:32 -05:00
Tyler Stachecki
b5ff809881 Add an implementation of VMADN. 2014-11-02 22:31:58 -05:00
Tyler Stachecki
bf197cf3bd Implement VMUDL, VMUDM, VMUDN. 2014-11-02 12:44:19 -05:00
Tyler Stachecki
304f667674 Implement several LWC2/SWC2 opcodes. 2014-10-25 14:03:26 -04:00
Tyler Stachecki
0c64ae620b Combine SLL, SLLV function logic. 2014-10-25 13:01:20 -04:00
Tyler Stachecki
85a21616cc Micro-optimization: faster li emulation. 
If we think about how the assembler forms 32-bit immediates, it
usually generates a lui and addiu pair. Well, if can craft the
simulation such that lui and addiu are the same indirect target
when branching to execution functions, we can reduce the chance
that we'll mispredict and have a resulting pipeline flush on the
host.

Every cycle counts!
 2014-10-25 12:40:27 -04:00
Tyler Stachecki
74327ef79e Compress LQV/SQV into one function. 2014-10-24 23:56:42 -04:00
Tyler Stachecki
e63b13605e Various LWC2/SWC2 fixes, add VSAR. 2014-10-24 21:07:25 -04:00
Tyler Stachecki
f395be631e Start adding in support for LWC2/SWC2 ops: LQV/SQV. 2014-10-24 18:31:13 -04:00
Tyler Stachecki
519f59f429 Start implementing some vector operators. 2014-10-22 18:15:44 -04:00
Tyler Stachecki
749b3906c9 Fix RSP DMEM endian issues and load-use code. 2014-10-18 12:26:03 -04:00
Tyler Stachecki
4ff41a0e34 Fix DMA/interrupt issues with the RSP. 2014-10-18 11:34:02 -04:00
Tyler Stachecki
7ac625cec1 Implement RSP DMAs, COP0 registers, etc. 2014-10-18 11:32:51 -04:00
Tyler Stachecki
440c51fef2 Add modified functions for RSP. 2014-10-18 11:32:43 -04:00
Tyler Stachecki
71961f0b00 Implement the RSP decoder. 2014-10-18 11:32:36 -04:00