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44 commits

Author SHA1 Message Date
Tyler J. Stachecki
3565a05f30 rsp: Use host byte ordering for ICACHE. 
Up until the, the RSP was storing instruction words in big-
endian format. Thus, each fetch on an x86 host requires a
byteswap. This is wasteful, so use host byte ordering for
the ICACHE (as the VR4300 does now).
 2016-02-27 19:13:50 -05:00
Tyler J. Stachecki
e2e72821e2 Try to reduce component cycle overheads. 
Oftentimes, many of our countrollers are just doing a
simple countdown and don't perform any real work for the
cycle. Pull those parts out into headers so that the
compiler can 'see' that and optimize accordingly.
 2016-01-30 14:58:31 -05:00
Derek "Turtle" Roe
8b89df2fdc See long description 
Replaced all references to simulation with emulation
Updated copyright year
Updated .gitignore to reduce chances of random files being uploaded to
the repo
Added .gitattributes to normalize all text files, and to ignore binary
files (which includes the logo and the NEC PDF)
 2015-07-01 18:44:21 -05:00
Tyler Stachecki
3cc07a7ae4 Unroll the top-level hot functions. 2015-01-22 14:31:54 -05:00
Tyler Stachecki
acd03ec4c6 RSP: Add an opcode cache for performance. 2015-01-09 23:22:39 -05:00
Tyler Stachecki
2c94219a9b RSP: Fix scalar load-use stall. 2015-01-09 23:22:32 -05:00
Tyler Stachecki
79b02e4702 RSP: Optimize memory requests slightly. 2015-01-09 23:22:26 -05:00
Tyler Stachecki
28196d2076 RSP: Optimize decoder/stall checks slightly. 2015-01-09 23:22:20 -05:00
Tyler Stachecki
321cf584f0 Remove some hacks from the RSP pipeline. 2015-01-08 12:17:06 -05:00
Tyler Stachecki
cc3aff976c Add 64DD mappings and a controller. 2015-01-06 14:07:45 -05:00
Tyler Stachecki
e63f8b08e3 Perform some really clever branch folding. 
Fold all the integer loads and stores into one code path.
 2015-01-06 02:18:31 -05:00
Tyler Stachecki
ec3748f0c2 Trim off a few hundred bytes of code. 2015-01-05 22:59:52 -05:00
Tyler Stachecki
c7a4a43242 Same as the last commit, but with the RSP. 2015-01-05 22:12:44 -05:00
Tyler Stachecki
b52962aa19 Fix RSP bug that arises on BREAK. 2015-01-01 10:46:48 -05:00
Tyler Stachecki
5e313634d3 Enable register-caching on MinGW. 
Use a prelude to get around Microsoft's stupid calling convention.
 2015-01-01 10:46:10 -05:00
Tyler Stachecki
9b941eced8 Change RSP calling convention. 
pblendvb needs the mask in %xmm0, so change the calling convention
around just enough so we can cut out a movdqa from most instructions.
 2015-01-01 10:44:34 -05:00
Tyler Stachecki
9f9e3ebf80 Sort out a pair of RSP bugs. 2014-12-26 14:19:45 -05:00
Tyler Stachecki
b33f2800ae Add implementation for MFC2. 2014-12-26 14:19:45 -05:00
Tyler Stachecki
824131db6b Use a union for RSP vectors to force alignment. 2014-12-26 14:19:45 -05:00
Tyler Stachecki
dc008abe77 Fix more show-stopping RSP bugs. 2014-12-26 14:19:45 -05:00
Tyler Stachecki
1e059e3f71 Fix a potentially disasterous RSP bug. 2014-12-26 14:19:45 -05:00
Tyler Stachecki
645f4b06ea Minor cleanup to the RSP pipeline. 2014-12-26 14:19:45 -05:00
Tyler Stachecki
6faca60054 Start reworking RSP vector loads and stores. 2014-12-26 14:19:45 -05:00
Tyler Stachecki
2ee295a671 Fix RSP DMEM accesses. 
Up until now, the simulator assumed that DMEM accesses had to be
aligned (similarly to the VR4300). This is not actually the case,
so allow scalar memory access to arbitrary DMEM addresses.
 2014-12-22 23:53:13 -05:00
Tyler Stachecki
c72f2c5028 Fix RSP alignment issues once and for all. 2014-12-19 20:03:03 -05:00
Tyler Stachecki
b4b95d1f21 Fix SS2 RSP vector loads/stores implementation. 2014-11-10 18:32:12 -05:00
Tyler Stachecki
3a24a67f1f Fix poor SSE2-based RSP performance. 2014-11-10 11:02:57 -05:00
Tyler Stachecki
d4a8f82b10 Change the RSP vector calling convention. 2014-11-02 22:45:33 -05:00
Tyler Stachecki
89ecd417d8 Pack RSP results into a result structure. 2014-11-02 13:40:49 -05:00
Tyler Stachecki
f6c77de8ea Fix an annoying little load-aligner bug. 2014-11-02 11:53:39 -05:00
Tyler Stachecki
c522b7cab0 Some minor tweaks/fixes to the SU pipeline. 2014-10-25 17:11:45 -04:00
Tyler Stachecki
e698bfe1d1 Improving accuracy of RSP LWC2/SWC2 operations. 2014-10-25 02:06:30 -04:00
Tyler Stachecki
e63b13605e Various LWC2/SWC2 fixes, add VSAR. 2014-10-24 21:07:25 -04:00
Tyler Stachecki
f395be631e Start adding in support for LWC2/SWC2 ops: LQV/SQV. 2014-10-24 18:31:13 -04:00
Tyler Stachecki
519f59f429 Start implementing some vector operators. 2014-10-22 18:15:44 -04:00
Tyler Stachecki
ab8687e263 Remove an unnecessary pair of RF writes. 
We always write to $0 during bypass logic to make sure that a
forwarded value, regardless of it's desination, never alters the
value of $0. Therefore, writing it to the RF as shown here is not
strictly necessary.
 2014-10-20 07:42:07 -04:00
Tyler Stachecki
69b810cfaa Silence an unused variable warning. 2014-10-18 12:31:28 -04:00
Tyler Stachecki
9dc2a36313 Remove some RSP debugging code and sloppyness. 2014-10-18 12:30:36 -04:00
Tyler Stachecki
749b3906c9 Fix RSP DMEM endian issues and load-use code. 2014-10-18 12:26:03 -04:00
Tyler Stachecki
421b0e0519 Implement some RSP DMEM reads and writes. 2014-10-18 11:34:09 -04:00
Tyler Stachecki
f5dc940dee Prevent the RSP from hanging the IPL. 2014-10-18 11:33:51 -04:00
Tyler Stachecki
0eea4f213e Start fleshing out the RSP backend. 2014-10-18 11:33:44 -04:00
Tyler Stachecki
b421093700 Start fleshing out the RSP frontend. 2014-10-18 11:33:14 -04:00
Tyler Stachecki
f520f6e9b8 Start fleshing out the RSP pipeline. 2014-10-18 11:33:04 -04:00