Commit graph

21 commits

Author SHA1 Message Date
Tyler J. Stachecki
3a11c666c9 rdp: Revert DPC_CLOCK_REG count commit. 2016-07-18 01:58:27 -04:00
Tyler Stachecki
18ff341415 rdp: Fix the frameskipping problem.
Don't let the RDP get too far ahead of the other cores or
it causes lots of frameskipping issues. Unfortunately, this
also hurts the performance but such is life.
2016-07-18 01:48:57 -04:00
Tyler J. Stachecki
618decfdeb rdp: Step DPC_CLOCK_REG even when RSP is halted. 2016-07-17 20:56:35 -04:00
Tyler J. Stachecki
e2e72821e2 Try to reduce component cycle overheads.
Oftentimes, many of our countrollers are just doing a
simple countdown and don't perform any real work for the
cycle. Pull those parts out into headers so that the
compiler can 'see' that and optimize accordingly.
2016-01-30 14:58:31 -05:00
Derek "Turtle" Roe
8b89df2fdc See long description
Replaced all references to simulation with emulation
Updated copyright year
Updated .gitignore to reduce chances of random files being uploaded to
the repo
Added .gitattributes to normalize all text files, and to ignore binary
files (which includes the logo and the NEC PDF)
2015-07-01 18:44:21 -05:00
Tyler Stachecki
1ba67eec9d Alignment/size optimizations. 2015-01-28 22:41:07 -05:00
Tyler Stachecki
3cc07a7ae4 Unroll the top-level hot functions. 2015-01-22 14:31:54 -05:00
Tyler Stachecki
acd03ec4c6 RSP: Add an opcode cache for performance. 2015-01-09 23:22:39 -05:00
Tyler Stachecki
321cf584f0 Remove some hacks from the RSP pipeline. 2015-01-08 12:17:06 -05:00
Tyler Stachecki
742ffc1493 Fix a series of RSP bugs that krom pointed out. 2015-01-01 21:13:41 -05:00
Tyler Stachecki
c72f2c5028 Fix RSP alignment issues once and for all. 2014-12-19 20:03:03 -05:00
Tyler Stachecki
8b45d7eab5 Fix padding around SSE register types.
Really need to stop doing patchjobs and just fix this.
2014-11-16 14:27:43 -05:00
Tyler Stachecki
c1dc7cba08 Refactor for another major performance boost.
Since the CEN64 core now runs in it's own thread (and doesn't use
the FPU), we can steal the host's FPU state register and not have
to worry about preserving it.

Along with that major overhaul, don't force "extra" features like
simulation statistics and debugging if the user doesn't want them.
Including that code, even when it is not run, mucks with register
allocation or something ever so slightly.
2014-11-15 18:22:20 -05:00
Tyler Stachecki
316214d82d (Finally) permit SSE2-only builds.
Add SSE2 codepaths where necessary (even if not complete), while
still allowing the project to be compiled with SSSE3+ intrinsics.
2014-11-10 14:29:13 -05:00
Tyler Stachecki
e89f054674 Optimize extremely aggressively.
Tell GCC to optimize cold functions for size and stash them away in
a separate part of the binary. Put the simulate core, meanwhile, on
the hot path. Also, bump optimization to -O3 as we can now "afford"
to do so.
2014-11-05 08:39:47 -05:00
Tyler Stachecki
f395be631e Start adding in support for LWC2/SWC2 ops: LQV/SQV. 2014-10-24 18:31:13 -04:00
Tyler Stachecki
519f59f429 Start implementing some vector operators. 2014-10-22 18:15:44 -04:00
Tyler Stachecki
7ac625cec1 Implement RSP DMAs, COP0 registers, etc. 2014-10-18 11:32:51 -04:00
Tyler Stachecki
440c51fef2 Add modified functions for RSP. 2014-10-18 11:32:43 -04:00
Tyler Stachecki
d114038a2b Add option for debugging MMIO register access. 2014-04-18 12:44:57 -04:00
Tyler Stachecki
4560adf7a7 Populate with interfaces and devices. 2014-04-18 11:24:43 -04:00