mirror of
https://github.com/devinacker/bsnes-plus.git
synced 2025-04-02 10:52:46 -04:00
443 lines
9.4 KiB
C++
443 lines
9.4 KiB
C++
#ifdef CX4_CPP
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void Cx4::push() {
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stack[7] = stack[6];
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stack[6] = stack[5];
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stack[5] = stack[4];
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stack[4] = stack[3];
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stack[3] = stack[2];
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stack[2] = stack[1];
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stack[1] = stack[0];
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stack[0] = regs.pc;
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}
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void Cx4::pull() {
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regs.pc = stack[0];
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stack[0] = stack[1];
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stack[1] = stack[2];
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stack[2] = stack[3];
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stack[3] = stack[4];
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stack[4] = stack[5];
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stack[5] = stack[6];
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stack[6] = stack[7];
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stack[7] = 0x0000;
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}
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//Shift-A: math opcodes can shift A register prior to ALU operation
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unsigned Cx4::sa() {
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switch(opcode & 0x0300) { default:
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case 0x0000: return regs.a << 0;
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case 0x0100: return regs.a << 1;
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case 0x0200: return regs.a << 8;
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case 0x0300: return regs.a << 16;
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}
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}
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//Register-or-Immediate: most opcodes can load from a register or immediate
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unsigned Cx4::ri() {
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if(opcode & 0x0400) return opcode & 0xff;
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return register_read(opcode & 0xff);
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}
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//New-PC: determine jump target address; opcode.d9 = long jump flag (1 = yes)
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unsigned Cx4::np() {
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if(opcode & 0x0200) return (regs.p << 8) | (opcode & 0xff);
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return (regs.pc & 0xffff00) | (opcode & 0xff);
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}
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void Cx4::instruction() {
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if((opcode & 0xfc00) == 0x0000) {
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//0000 00.. .... ....
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//nop
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}
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else if((opcode & 0xdd00) == 0x0800) {
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//00.0 10.0 .... ....
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//jump i
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if(opcode & 0x2000) push();
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regs.pc = np();
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change_page();
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add_clocks(2);
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}
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else if((opcode & 0xdd00) == 0x0c00) {
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//00.0 11.0 .... ....
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//jumpeq i
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if(regs.z) {
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if(opcode & 0x2000) push();
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regs.pc = np();
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change_page();
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add_clocks(2);
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}
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}
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else if((opcode & 0xdd00) == 0x1000) {
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//00.1 00.0 .... ....
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//jumpge i
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if(regs.c) {
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if(opcode & 0x2000) push();
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regs.pc = np();
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change_page();
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add_clocks(2);
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}
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}
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else if((opcode & 0xdd00) == 0x1400) {
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//00.1 01.0 .... ....
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//jumpmi i
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if(regs.n) {
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if(opcode & 0x2000) push();
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regs.pc = np();
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change_page();
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add_clocks(2);
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}
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}
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else if((opcode & 0xdd00) == 0x1800) {
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//00.1 10.0 .... ....
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//jumpvs i
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if(regs.v) {
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if(opcode & 0x2000) push();
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regs.pc = np();
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change_page();
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add_clocks(2);
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}
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}
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else if((opcode & 0xfc00) == 0x1c00) {
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//0001 11.. .... ....
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//loop
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if (regs.rwbustime > 1) {
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add_clocks(regs.rwbustime - 1);
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}
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}
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else if((opcode & 0xff00) == 0x2400) {
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//0010 0100 .... ....
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//skipvc/skipvs
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if(regs.v == (opcode & 1)) {
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nextpc();
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add_clocks(1);
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}
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}
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else if((opcode & 0xff00) == 0x2500) {
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//0010 0101 .... ....
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//skiplt/skipge
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if(regs.c == (opcode & 1)) {
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nextpc();
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add_clocks(1);
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}
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}
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else if((opcode & 0xff00) == 0x2600) {
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//0010 0110 .... ....
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//skipne/skipeq
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if(regs.z == (opcode & 1)) {
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nextpc();
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add_clocks(1);
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}
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}
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else if((opcode & 0xff00) == 0x2700) {
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//0010 0111 .... ....
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//skipmi/skippl
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if(regs.n == (opcode & 1)) {
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nextpc();
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add_clocks(1);
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}
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}
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else if((opcode & 0xfc00) == 0x3c00) {
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//0011 11.. .... ....
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//ret
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pull();
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change_page();
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add_clocks(2);
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}
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else if((opcode & 0xfc00) == 0x4000) {
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//0100 00.. .... ....
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//inc
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regs.busaddr++;
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}
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else if((opcode & 0xf800) == 0x4800) {
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//0100 1... .... ....
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//cmpr a<<n,ri
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int result = ri() - sa();
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regs.n = result & 0x800000;
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regs.z = (uint24)result == 0;
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regs.c = result >= 0;
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}
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else if((opcode & 0xf800) == 0x5000) {
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//0101 0... .... ....
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//cmp a<<n,ri
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int result = sa() - ri();
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regs.n = result & 0x800000;
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regs.z = (uint24)result == 0;
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regs.c = result >= 0;
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}
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else if((opcode & 0xfb00) == 0x5900) {
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//0101 1.01 .... ....
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//sxb
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regs.a = (int8)ri();
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}
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else if((opcode & 0xfb00) == 0x5a00) {
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//0101 1.10 .... ....
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//sxw
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regs.a = (int16)ri();
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}
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else if((opcode & 0xfb00) == 0x6000) {
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//0110 0.00 .... ....
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//ld a,ri
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regs.a = ri();
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}
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else if((opcode & 0xfb00) == 0x6100) {
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//0110 0.01 .... ....
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//rdbus r
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register_read(opcode & 0xff);
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}
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else if((opcode & 0xfb00) == 0x6300) {
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//0110 0.11 .... ....
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//ld p,ri
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regs.p = ri();
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}
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else if((opcode & 0xfb00) == 0x6800) {
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//0110 1.00 .... ....
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//rdraml
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uint24 target = ri() + (opcode & 0x0400 ? regs.ramaddr : (uint24)0);
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if(target < 0xc00) {
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regs.ramdata = (regs.ramdata & 0xffff00) | (dataRAM[target] << 0);
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regs.mdr = regs.ramdata;
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}
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}
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else if((opcode & 0xfb00) == 0x6900) {
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//0110 1.01 .... ....
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//rdramh
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uint24 target = ri() + (opcode & 0x0400 ? regs.ramaddr : (uint24)0);
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if(target < 0xc00) {
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regs.ramdata = (regs.ramdata & 0xff00ff) | (dataRAM[target] << 8);
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regs.mdr = regs.ramdata;
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}
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}
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else if((opcode & 0xfb00) == 0x6a00) {
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//0110 1.10 .... ....
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//rdramb
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uint24 target = ri() + (opcode & 0x0400 ? regs.ramaddr : (uint24)0);
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if(target < 0xc00) {
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regs.ramdata = (regs.ramdata & 0x00ffff) | (dataRAM[target] << 16);
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regs.mdr = regs.ramdata;
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}
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}
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else if((opcode & 0xffff) == 0x7000) {
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//0111 0000 0000 0000
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//rdrom
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regs.romdata = dataROM[regs.a & 0x3ff];
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}
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else if((opcode & 0xff00) == 0x7c00) {
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//0111 1100 .... ....
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//ld pl,i
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regs.p = (regs.p & 0xff00) | ((opcode & 0xff) << 0);
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}
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else if((opcode & 0xff00) == 0x7d00) {
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//0111 1101 .... ....
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//ld ph,i
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regs.p = (regs.p & 0x00ff) | ((opcode & 0xff) << 8);
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}
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else if((opcode & 0xf800) == 0x8000) {
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//1000 0... .... ....
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//add a<<n,ri
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int x = sa();
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int y = ri();
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int result = x + y;
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regs.a = result;
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regs.n = regs.a & 0x800000;
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regs.z = regs.a == 0;
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regs.c = result > 0xffffff;
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regs.v = ~(x & y) & (x ^ result) & (1 << 23);
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}
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else if((opcode & 0xf800) == 0x8800) {
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//1000 1... .... ....
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//subr a<<n,ri
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int x = ri();
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int y = sa();
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int result = x - y;
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regs.a = result;
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regs.n = regs.a & 0x800000;
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regs.z = regs.a == 0;
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regs.c = result >= 0;
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regs.v = ~(x & y) & (x ^ result) & (1 << 23);
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}
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else if((opcode & 0xf800) == 0x9000) {
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//1001 0... .... ....
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//sub a<<n,ri
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int x = sa();
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int y = ri();
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int result = x - y;
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regs.a = result;
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regs.n = regs.a & 0x800000;
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regs.z = regs.a == 0;
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regs.c = result >= 0;
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regs.v = ~(x & y) & (x ^ result) & (1 << 23);
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}
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else if((opcode & 0xfb00) == 0x9800) {
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//1001 1.00 .... ....
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//mul a,ri
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int64 x = (int24)regs.a;
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int64 y = (int24)ri();
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x *= y;
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regs.accl = x >> 0ull;
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regs.acch = x >> 24ull;
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regs.n = regs.acch & 0x800000;
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regs.z = x == 0;
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}
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else if((opcode & 0xf800) == 0xa800) {
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//1010 1... .... ....
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//xor a<<n,ri
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regs.a = sa() ^ ri();
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regs.n = regs.a & 0x800000;
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regs.z = regs.a == 0;
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}
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else if((opcode & 0xf800) == 0xb000) {
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//1011 0... .... ....
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//and a<<n,ri
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regs.a = sa() & ri();
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regs.n = regs.a & 0x800000;
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regs.z = regs.a == 0;
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}
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else if((opcode & 0xf800) == 0xb800) {
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//1011 1... .... ....
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//or a<<n,ri
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regs.a = sa() | ri();
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regs.n = regs.a & 0x800000;
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regs.z = regs.a == 0;
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}
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else if((opcode & 0xfb00) == 0xc000) {
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//1100 0.00 .... ....
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//shr a,ri
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regs.a = regs.a >> ri();
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regs.n = regs.a & 0x800000;
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regs.z = regs.a == 0;
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}
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else if((opcode & 0xfb00) == 0xc800) {
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//1100 1.00 .... ....
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//asr a,ri
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regs.a = (int24)regs.a >> ri();
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regs.n = regs.a & 0x800000;
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regs.z = regs.a == 0;
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}
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else if((opcode & 0xfb00) == 0xd000) {
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//1101 0.00 .... ....
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//ror a,ri
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uint24 length = ri();
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regs.a = (regs.a >> length) | (regs.a << (24 - length));
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regs.n = regs.a & 0x800000;
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regs.z = regs.a == 0;
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}
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else if((opcode & 0xfb00) == 0xd800) {
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//1101 1.00 .... ....
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//shl a,ri
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regs.a = regs.a << ri();
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regs.n = regs.a & 0x800000;
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regs.z = regs.a == 0;
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}
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else if((opcode & 0xff00) == 0xe000) {
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//1110 0000 .... ....
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//st r,a
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register_write(opcode & 0xff, regs.a);
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}
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else if((opcode & 0xff00) == 0xe1000) {
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//1110 0001 .... ....
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//wrbus r
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register_write(opcode & 0xff, regs.busdata);
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}
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else if((opcode & 0xfb00) == 0xe800) {
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//1110 1.00 .... ....
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//wrraml
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uint24 target = ri() + (opcode & 0x0400 ? regs.ramaddr : (uint24)0);
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if(target < 0xc00) {
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dataRAM[target] = regs.ramdata >> 0;
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regs.mdr = regs.ramdata;
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}
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}
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else if((opcode & 0xfb00) == 0xe900) {
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//1110 1.01 .... ....
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//wrramh
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uint24 target = ri() + (opcode & 0x0400 ? regs.ramaddr : (uint24)0);
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if(target < 0xc00) {
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dataRAM[target] = regs.ramdata >> 8;
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regs.mdr = regs.ramdata;
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}
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}
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else if((opcode & 0xfb00) == 0xea00) {
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//1110 1.10 .... ....
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//wrramb
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uint24 target = ri() + (opcode & 0x0400 ? regs.ramaddr : (uint24)0);
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if(target < 0xc00) {
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dataRAM[target] = regs.ramdata >> 16;
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regs.mdr = regs.ramdata;
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}
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}
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else if((opcode & 0xfc00) == 0xf000) {
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//1111 00.. .... ....
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//swap a,r
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uint24 source = register_read(opcode & 0xff);
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uint24 target = regs.a;
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regs.a = source;
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register_write(opcode & 0xff, target);
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}
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else if((opcode & 0xfc00) == 0xf800) {
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//1111 10.. .... ....
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//clear
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regs.a = 0;
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regs.p = 0;
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regs.ramdata = 0;
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regs.ramaddr = 0;
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}
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else if((opcode & 0xfc00) == 0xfc00) {
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//1111 11.. .... ....
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//halt
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regs.halt = true;
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}
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else {
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// unknown opcode
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regs.halt = true;
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}
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add_clocks(1);
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}
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#endif
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