mirror of
https://github.com/devinacker/bsnes-plus.git
synced 2025-04-02 10:52:46 -04:00
127 lines
3.3 KiB
C++
127 lines
3.3 KiB
C++
#ifdef SUPERGAMEBOY_CPP
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uint16 SGBDebugger::relb(int8 offset, int op_len, uint16 pc) {
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return pc + op_len + offset;
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}
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uint8 SGBDebugger::dreadb(uint16 addr) {
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SNES::debugger.bus_access = true;
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return supergameboy.read_gb(addr);
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SNES::debugger.bus_access = false;
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}
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uint16 SGBDebugger::dreadw(uint16 addr) {
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uint16 r;
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r = dreadb(addr + 0) << 0;
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r |= dreadb(addr + 1) << 8;
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return r;
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}
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uint24 SGBDebugger::decode(uint8 offset_type, uint16 addr, uint16 pc) {
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uint24 r = 0;
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uint16 dp = 0xff00;
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switch(offset_type) {
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case GBCPU::Addr8Ptr:
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r = dp | (uint8)addr;
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break;
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case GBCPU::Addr16:
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case GBCPU::Addr16Ptr:
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r = addr;
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break;
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case GBCPU::RegBCPtr:
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r = getRegister(RegisterBC);
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break;
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case GBCPU::RegCPtr:
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r = dp | (uint8)getRegister(RegisterBC);
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break;
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case GBCPU::RegDEPtr:
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r = getRegister(RegisterDE);
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break;
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case GBCPU::RegHLPtr:
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case GBCPU::RegHLPtrInc:
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case GBCPU::RegHLPtrDec:
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case GBCPU::PrefixCB:
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r = getRegister(RegisterHL);
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break;
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case GBCPU::PCRelative:
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r = relb((int8)addr, 2, pc);
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break;
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case GBCPU::SPRelative:
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r = relb((int8)addr, 2, getRegister(RegisterSP));
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break;
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case GBCPU::RST:
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r = dreadb(pc) & 0x38;
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break;
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}
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if (r > 0x4000 && sgb_addr_with_bank) {
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r = sgb_addr_with_bank(r);
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}
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return r;
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}
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void SGBDebugger::disassemble_opcode_ex(SGBDebugger::Opcode &opcode, uint24 addr) {
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uint8 param[3];
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SNES::debugger.bus_access = true;
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param[0] = read_gb(addr + 0);
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param[1] = read_gb(addr + 1);
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param[2] = read_gb(addr + 2);
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SNES::debugger.bus_access = false;
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const GBCPU::OpcodeInfo& op = gbOpcodeInfo[param[0]];
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opcode.set(0, op.mode0, op.mode1, op.name, param, GBCPU::getOpcodeLength(param[0]) - 1);
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switch (param[0]) {
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case 0x18: case 0xc3: case 0xe9:
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opcode.flags |= Opcode::FLAG_BRA; break;
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case 0x20: case 0x28: case 0x30: case 0x38:
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case 0xc2: case 0xca: case 0xd2: case 0xda:
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opcode.flags |= Opcode::FLAG_BRA_CONTINUE; break;
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case 0xc4: case 0xc7: case 0xcc: case 0xcd:
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case 0xcf: case 0xd4: case 0xd7: case 0xdc:
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case 0xdf: case 0xe7: case 0xef: case 0xf7:
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case 0xff:
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opcode.flags |= Opcode::FLAG_CALL; break;
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case 0xc9: case 0xd9:
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opcode.flags |= Opcode::FLAG_RETURN; break;
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case 0xf1:
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opcode.flags |= Opcode::FLAG_POP_F; break;
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case 0xf5:
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opcode.flags |= Opcode::FLAG_PUSH_F; break;
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}
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if (GBCPU::getOpcodeIndirect(param[0], param[1])) {
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opcode.flags |= Opcode::FLAG_INDIRECT;
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}
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}
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void SGBDebugger::disassemble_opcode(char *output, uint24 addr) {
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char t[256];
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char *s = output;
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sprintf(s, "%.6x ", addr);
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uint8 op = read_gb(addr);
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uint8 op0 = read_gb(addr + 1);
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uint8 op1 = read_gb(addr + 2);
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sprintf(t, "%-23s ", nall::GBCPU::disassemble((uint16)addr, op, op0, op1)());
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strcat(s, t);
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uint16_t af = getRegister(RegisterAF);
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uint16_t bc = getRegister(RegisterBC);
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uint16_t de = getRegister(RegisterDE);
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uint16_t hl = getRegister(RegisterHL);
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uint16_t sp = getRegister(RegisterSP);
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sprintf(t, "AF:%.4x BC:%.4x DE:%.4x HL:%.4x SP:%.4x ", af, bc, de, hl, sp);
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strcat(s, t);
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sprintf(t, "%c%c%c%c ",
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(af & 0x80) ? 'Z' : '.', (af & 0x40) ? 'N' : '.',
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(af & 0x20) ? 'H' : '.', (af & 0x10) ? 'C' : '.');
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strcat(s, t);
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}
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#endif
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