mirror of
https://github.com/SourMesen/Mesen2.git
synced 2025-04-02 10:21:44 -04:00
9a38d6cff4
Save state from power on would save the cycle count as 4, but the code in UpdateClockRatio would set it to 17, causing movies to potentially desync because the SPC and CPU aren't running with the same "alignment" they had when the movie was recorded
593 lines
No EOL
13 KiB
C++
593 lines
No EOL
13 KiB
C++
#include "pch.h"
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#include "SNES/Spc.h"
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#include "SNES/SnesConsole.h"
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#include "SNES/SnesMemoryManager.h"
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#include "SNES/SpcFileData.h"
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#ifndef DUMMYSPC
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#include "SNES/DSP/Dsp.h"
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#else
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#undef Spc
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#undef DUMMYSPC
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#include "SNES/DSP/Dsp.h"
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#define Spc DummySpc
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#define DUMMYSPC
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#endif
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#include "Shared/Emulator.h"
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#include "Shared/EmuSettings.h"
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#include "Shared/Audio/SoundMixer.h"
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#include "Utilities/Serializer.h"
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#include "Shared/MemoryOperationType.h"
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Spc::Spc(SnesConsole* console)
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{
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_emu = console->GetEmulator();
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_console = console;
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_memoryManager = console->GetMemoryManager();
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_ram = new uint8_t[Spc::SpcRamSize];
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_emu->RegisterMemory(MemoryType::SpcRam, _ram, Spc::SpcRamSize);
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_console->InitializeRam(_ram, Spc::SpcRamSize);
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_emu->RegisterMemory(MemoryType::SpcRom, _spcBios, Spc::SpcRomSize);
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#ifndef DUMMYSPC
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_dsp.reset(new Dsp(_emu, this));
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#endif
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_state = {};
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_state.WriteEnabled = true;
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_state.TimersEnabled = true;
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_state.RomEnabled = true;
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_state.SP = 0xFF;
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_state.PC = ReadWord(Spc::ResetVector);
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_state.StopState = SnesCpuStopState::Running;
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_opCode = 0;
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_opStep = SpcOpStep::ReadOpCode;
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_opSubStep = 0;
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_tmp1 = 0;
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_tmp2 = 0;
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_tmp3 = 0;
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_operandA = 0;
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_operandB = 0;
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_enabled = true;
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UpdateClockRatio();
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}
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#ifndef DUMMYSPC
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Spc::~Spc()
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{
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delete[] _ram;
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}
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#endif
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void Spc::Reset()
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{
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_state.StopState = SnesCpuStopState::Running;
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_state.Timer0.Reset();
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_state.Timer1.Reset();
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_state.Timer2.Reset();
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//Resetting appears to reset the values the main CPU can read (not doing this causes a freeze in Kaite Tsukette Asoberu Dezaemon)
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_state.OutputReg[0] = 0;
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_state.OutputReg[1] = 0;
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_state.OutputReg[2] = 0;
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_state.OutputReg[3] = 0;
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_state.RomEnabled = true;
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_state.Cycle = 0;
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_state.PC = ReadWord(Spc::ResetVector);
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_state.A = 0;
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_state.X = 0;
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_state.Y = 0;
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_state.SP = 0xFF;
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//Clear P (and other flags) - if P is set after reset, the IPL ROM doesn't work properly
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_state.PS = 0;
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_opCode = 0;
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_opStep = SpcOpStep::ReadOpCode;
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_opSubStep = 0;
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_tmp1 = 0;
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_tmp2 = 0;
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_tmp3 = 0;
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_operandA = 0;
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_operandB = 0;
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_dsp->Reset();
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}
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void Spc::SetSpcState(bool enabled)
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{
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//Used by overclocking logic to disable SPC during the extra scanlines added to the PPU
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if(_enabled != enabled) {
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if(enabled) {
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//When re-enabling, adjust the cycle counter to prevent running extra cycles
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UpdateClockRatio();
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} else {
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//Catch up SPC before disabling it
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Run();
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}
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_enabled = enabled;
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}
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}
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void Spc::UpdateClockRatio()
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{
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_clockRatio = (double)(Spc::SpcSampleRate * 64) / _console->GetMasterClockRate();
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//If the target cycle is off by more than 20 cycles, reset the counter to match what was expected
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//This can happen due to overclocking (which disables the SPC for some scanlines) or if the SPC's
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//internal sample rate is changed between versions (e.g 32000hz -> 32040hz)
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uint64_t targetCycle = (uint64_t)(_memoryManager->GetMasterClock() * _clockRatio);
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if(std::abs((int64_t)targetCycle - (int64_t)_state.Cycle) > 20) {
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_state.Cycle = targetCycle;
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}
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}
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void Spc::Idle()
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{
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IncCycleCount(-1);
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}
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void Spc::DummyRead()
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{
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Read(_state.PC, MemoryOperationType::DummyRead);
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}
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void Spc::DummyRead(uint16_t addr)
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{
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Read(addr, MemoryOperationType::DummyRead);
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}
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void Spc::IncCycleCount(int32_t addr)
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{
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static constexpr uint8_t cpuWait[4] = { 2, 4, 10, 20 };
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static constexpr uint8_t timerMultiplier[4] = { 2, 4, 8, 16 };
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uint8_t speedSelect;
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if(addr < 0 || ((addr & 0xFFF0) == 0x00F0) || (addr >= 0xFFC0 && _state.RomEnabled)) {
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//Use internal speed (bits 4-5) for idle cycles, register access or IPL rom access
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speedSelect = _state.InternalSpeed;
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} else {
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speedSelect = _state.ExternalSpeed;
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}
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_state.Cycle += cpuWait[speedSelect];
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#ifndef DUMMYSPC
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_dsp->Exec();
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#endif
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uint8_t timerInc = timerMultiplier[speedSelect];
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_state.Timer0.Run(timerInc);
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_state.Timer1.Run(timerInc);
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_state.Timer2.Run(timerInc);
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}
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uint8_t Spc::DebugRead(uint16_t addr)
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{
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if(addr >= 0xFFC0 && _state.RomEnabled) {
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return _spcBios[addr & 0x3F];
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}
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switch(addr) {
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case 0xF0: return 0;
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case 0xF1: return 0;
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case 0xF2: return _state.DspReg;
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case 0xF3: return _dsp->Read(_state.DspReg & 0x7F);
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case 0xF4: return _state.CpuRegs[0];
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case 0xF5: return _state.CpuRegs[1];
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case 0xF6: return _state.CpuRegs[2];
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case 0xF7: return _state.CpuRegs[3];
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case 0xF8: return _state.RamReg[0];
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case 0xF9: return _state.RamReg[1];
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case 0xFA: return 0;
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case 0xFB: return 0;
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case 0xFC: return 0;
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case 0xFD: return _state.Timer0.DebugRead();
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case 0xFE: return _state.Timer1.DebugRead();
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case 0xFF: return _state.Timer2.DebugRead();
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default: return _ram[addr];
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}
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}
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void Spc::DebugWrite(uint16_t addr, uint8_t value)
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{
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_ram[addr] = value;
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}
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uint8_t Spc::Read(uint16_t addr, MemoryOperationType type)
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{
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IncCycleCount(addr);
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uint8_t value;
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if(addr >= 0xFFC0 && _state.RomEnabled) {
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value = _spcBios[addr & 0x3F];
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} else {
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switch(addr) {
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case 0xF0: value = 0; break;
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case 0xF1: value = 0; break;
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case 0xF2: value = _state.DspReg; break;
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case 0xF3:
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#ifndef DUMMYSPC
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value = _dsp->Read(_state.DspReg & 0x7F);
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#else
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value = 0;
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#endif
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break;
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case 0xF4: value = _state.CpuRegs[0]; break;
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case 0xF5: value = _state.CpuRegs[1]; break;
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case 0xF6: value = _state.CpuRegs[2]; break;
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case 0xF7: value = _state.CpuRegs[3]; break;
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case 0xF8: value = _state.RamReg[0]; break;
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case 0xF9: value = _state.RamReg[1]; break;
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case 0xFA: value = 0; break;
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case 0xFB: value = 0; break;
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case 0xFC: value = 0; break;
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case 0xFD: value = _state.Timer0.GetOutput(); break;
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case 0xFE: value = _state.Timer1.GetOutput(); break;
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case 0xFF: value = _state.Timer2.GetOutput(); break;
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default: value = _ram[addr]; break;
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}
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}
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#ifndef DUMMYSPC
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_emu->ProcessMemoryRead<CpuType::Spc>(addr, value, type);
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#else
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LogMemoryOperation(addr, value, type);
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#endif
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return value;
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}
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void Spc::Write(uint16_t addr, uint8_t value, MemoryOperationType type)
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{
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IncCycleCount(addr);
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#ifdef DUMMYSPC
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LogMemoryOperation(addr, value, type);
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#else
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//Writes always affect the underlying RAM
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if(_state.WriteEnabled) {
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_emu->ProcessMemoryWrite<CpuType::Spc>(addr, value, type);
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_ram[addr] = value;
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}
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switch(addr) {
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case 0xF0:
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if(!CheckFlag(SpcFlags::DirectPage)) {
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_state.InternalSpeed = (value >> 6) & 0x03;
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_state.ExternalSpeed = (value >> 4) & 0x03;
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_state.TimersEnabled = (value & 0x08) != 0;
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_state.TimersDisabled = (value & 0x01) != 0;
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_state.WriteEnabled = value & 0x02;
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bool timersEnabled = _state.TimersEnabled && !_state.TimersDisabled;
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_state.Timer0.SetGlobalEnabled(timersEnabled);
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_state.Timer1.SetGlobalEnabled(timersEnabled);
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_state.Timer2.SetGlobalEnabled(timersEnabled);
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}
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break;
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case 0xF1:
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if(value & SpcControlFlags::ClearPortsA) {
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_state.CpuRegs[0] = _state.CpuRegs[1] = 0;
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}
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if(value & SpcControlFlags::ClearPortsB) {
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_state.CpuRegs[2] = _state.CpuRegs[3] = 0;
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}
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_state.Timer0.SetEnabled((value & SpcControlFlags::Timer0) != 0);
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_state.Timer1.SetEnabled((value & SpcControlFlags::Timer1) != 0);
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_state.Timer2.SetEnabled((value & SpcControlFlags::Timer2) != 0);
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_state.RomEnabled = (value & SpcControlFlags::EnableRom) != 0;
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break;
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case 0xF2: _state.DspReg = value; break;
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case 0xF3:
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if(_state.DspReg < 128) {
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_dsp->Write(_state.DspReg, value);
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}
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break;
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case 0xF4: _state.OutputReg[0] = value; break;
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case 0xF5: _state.OutputReg[1] = value; break;
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case 0xF6: _state.OutputReg[2] = value; break;
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case 0xF7: _state.OutputReg[3] = value; break;
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case 0xF8: _state.RamReg[0] = value; break;
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case 0xF9: _state.RamReg[1] = value; break;
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case 0xFA: _state.Timer0.SetTarget(value); break;
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case 0xFB: _state.Timer1.SetTarget(value); break;
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case 0xFC: _state.Timer2.SetTarget(value); break;
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case 0xFD: break;
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case 0xFE: break;
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case 0xFF: break;
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}
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#endif
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}
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uint8_t Spc::CpuReadRegister(uint16_t addr)
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{
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Run();
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return _state.OutputReg[addr & 0x03];
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}
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void Spc::CpuWriteRegister(uint32_t addr, uint8_t value)
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{
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Run();
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_state.CpuRegs[addr & 0x03] = value;
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}
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uint8_t Spc::DspReadRam(uint16_t addr)
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{
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uint8_t value = _ram[addr];
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#ifndef DUMMYSPC
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//TODO
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//_emu->ProcessMemoryRead<CpuType::Spc>(addr, value, MemoryOperationType::Read);
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#endif
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return value;
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}
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void Spc::DspWriteRam(uint16_t addr, uint8_t value)
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{
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#ifndef DUMMYSPC
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//TODO
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//_emu->ProcessMemoryWrite<CpuType::Spc>(addr, value, MemoryOperationType::Write);
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#endif
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_ram[addr] = value;
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}
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void Spc::Run()
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{
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if(!_enabled || _state.StopState != SnesCpuStopState::Running) {
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//STOP or SLEEP were executed - execution is stopped forever.
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return;
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}
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uint64_t targetCycle = (uint64_t)(_memoryManager->GetMasterClock() * _clockRatio);
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while(_state.Cycle < targetCycle) {
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ProcessCycle();
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}
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}
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void Spc::ProcessCycle()
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{
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if(_opStep == SpcOpStep::ReadOpCode) {
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#ifndef DUMMYSPC
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_emu->ProcessInstruction<CpuType::Spc>();
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#endif
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_opCode = GetOpCode();
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_opStep = SpcOpStep::Addressing;
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_opSubStep = 0;
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} else {
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Exec();
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}
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}
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void Spc::ProcessEndFrame()
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{
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Run();
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UpdateClockRatio();
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uint16_t sampleCount = _dsp->GetSampleCount();
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if(sampleCount != 0) {
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_emu->GetSoundMixer()->PlayAudioBuffer(_dsp->GetSamples(), sampleCount / 2, Spc::SpcSampleRate);
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}
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_dsp->ResetOutput();
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}
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SpcState& Spc::GetState()
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{
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return _state;
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}
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DspState& Spc::GetDspState()
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{
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return _dsp->GetState();
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}
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bool Spc::IsMuted()
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{
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return _dsp->IsMuted();
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}
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AddressInfo Spc::GetAbsoluteAddress(uint16_t addr)
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{
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if(addr < 0xFFC0 || !_state.RomEnabled) {
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return AddressInfo { addr, MemoryType::SpcRam };
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}
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return AddressInfo { addr & 0x3F, MemoryType::SpcRom };
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}
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int Spc::GetRelativeAddress(AddressInfo &absAddress)
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{
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if(absAddress.Type == MemoryType::SpcRom) {
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if(_state.RomEnabled) {
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return 0xFFC0 | (absAddress.Address & 0x3F);
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}
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} else {
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if(absAddress.Address < 0xFFC0 || !_state.RomEnabled) {
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return absAddress.Address;
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}
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}
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return -1;
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}
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uint8_t* Spc::GetSpcRam()
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{
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return _ram;
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}
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uint8_t* Spc::GetSpcRom()
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{
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return _spcBios;
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}
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void Spc::Serialize(Serializer &s)
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{
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if(s.IsSaving()) {
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//Catch up SPC to main CPU before creating the state
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Run();
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}
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SV(_state.A); SV(_state.Cycle); SV(_state.PC); SV(_state.PS); SV(_state.SP); SV(_state.X); SV(_state.Y);
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SV(_state.CpuRegs[0]); SV(_state.CpuRegs[1]); SV(_state.CpuRegs[2]); SV(_state.CpuRegs[3]);
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SV(_state.OutputReg[0]); SV(_state.OutputReg[1]); SV(_state.OutputReg[2]); SV(_state.OutputReg[3]);
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SV(_state.RamReg[0]); SV(_state.RamReg[1]);
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SV(_state.ExternalSpeed); SV(_state.InternalSpeed); SV(_state.WriteEnabled); SV(_state.TimersEnabled);
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SV(_state.DspReg); SV(_state.RomEnabled); SV(_clockRatio); SV(_state.TimersDisabled);
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s.PushNamePrefix("timer0", -1);
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_state.Timer0.Serialize(s);
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s.PopNamePrefix();
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s.PushNamePrefix("timer1", -1);
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_state.Timer1.Serialize(s);
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s.PopNamePrefix();
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s.PushNamePrefix("timer2", -1);
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_state.Timer2.Serialize(s);
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s.PopNamePrefix();
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SVArray(_ram, Spc::SpcRamSize);
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SV(_dsp);
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if(!s.IsSaving()) {
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UpdateClockRatio();
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}
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if(s.GetFormat() != SerializeFormat::Map) {
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SV(_operandA); SV(_operandB); SV(_tmp1); SV(_tmp2); SV(_tmp3); SV(_opCode); SV(_opStep); SV(_opSubStep); SV(_enabled);
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}
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}
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uint8_t Spc::GetOpCode()
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{
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uint8_t value = Read(_state.PC, MemoryOperationType::ExecOpCode);
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_state.PC++;
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return value;
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}
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uint8_t Spc::ReadOperandByte()
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{
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uint8_t value = Read(_state.PC, MemoryOperationType::ExecOperand);
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_state.PC++;
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return value;
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}
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uint16_t Spc::ReadWord(uint16_t addr, MemoryOperationType type)
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{
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uint8_t lsb = Read(addr, type);
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uint8_t msb = Read(addr + 1, type);
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return (msb << 8) | lsb;
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}
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void Spc::ClearFlags(uint8_t flags)
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{
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_state.PS &= ~flags;
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}
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void Spc::SetFlags(uint8_t flags)
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{
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_state.PS |= flags;
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}
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bool Spc::CheckFlag(uint8_t flag)
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{
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return (_state.PS & flag) == flag;
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}
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void Spc::SetZeroNegativeFlags(uint8_t value)
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{
|
|
ClearFlags(SpcFlags::Zero | SpcFlags::Negative);
|
|
if(value == 0) {
|
|
SetFlags(SpcFlags::Zero);
|
|
} else if(value & 0x80) {
|
|
SetFlags(SpcFlags::Negative);
|
|
}
|
|
}
|
|
|
|
void Spc::SetZeroNegativeFlags16(uint16_t value)
|
|
{
|
|
ClearFlags(SpcFlags::Zero | SpcFlags::Negative);
|
|
if(value == 0) {
|
|
SetFlags(SpcFlags::Zero);
|
|
} else if(value & 0x8000) {
|
|
SetFlags(SpcFlags::Negative);
|
|
}
|
|
}
|
|
|
|
uint8_t Spc::GetByteValue()
|
|
{
|
|
return Read(_operandA);
|
|
}
|
|
|
|
void Spc::Push(uint8_t value)
|
|
{
|
|
Write(0x100 | _state.SP, value);
|
|
_state.SP--;
|
|
}
|
|
|
|
uint8_t Spc::Pop()
|
|
{
|
|
_state.SP++;
|
|
return Read(0x100 | _state.SP);
|
|
}
|
|
|
|
uint16_t Spc::GetDirectAddress(uint8_t offset)
|
|
{
|
|
return (CheckFlag(SpcFlags::DirectPage) ? 0x100 : 0) + offset;
|
|
}
|
|
|
|
void Spc::LoadSpcFile(SpcFileData* data)
|
|
{
|
|
memcpy(_ram, data->SpcRam, Spc::SpcRamSize);
|
|
|
|
memcpy(_dsp->GetState().Regs, data->DspRegs, sizeof(data->DspRegs));
|
|
|
|
_state.PC = data->PC;
|
|
_state.A = data->A;
|
|
_state.X = data->X;
|
|
_state.Y = data->Y;
|
|
_state.PS = data->PS;
|
|
_state.SP = data->SP;
|
|
|
|
Write(0xF1, data->ControlReg);
|
|
_state.DspReg = data->DspRegSelect;
|
|
|
|
_state.CpuRegs[0] = data->CpuRegs[0];
|
|
_state.CpuRegs[1] = data->CpuRegs[1];
|
|
_state.CpuRegs[2] = data->CpuRegs[2];
|
|
_state.CpuRegs[3] = data->CpuRegs[3];
|
|
|
|
_state.RamReg[0] = data->RamRegs[0];
|
|
_state.RamReg[1] = data->RamRegs[1];
|
|
|
|
_state.Timer0.SetTarget(data->TimerTarget[0]);
|
|
_state.Timer1.SetTarget(data->TimerTarget[1]);
|
|
_state.Timer2.SetTarget(data->TimerTarget[2]);
|
|
|
|
_state.Timer0.SetOutput(data->TimerOutput[0]);
|
|
_state.Timer1.SetOutput(data->TimerOutput[0]);
|
|
_state.Timer2.SetOutput(data->TimerOutput[0]);
|
|
} |