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SNES: Fixed SPC not being in the exact same alignment after loading a save state
Save state from power on would save the cycle count as 4, but the code in UpdateClockRatio would set it to 17, causing movies to potentially desync because the SPC and CPU aren't running with the same "alignment" they had when the movie was recorded
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1 changed files with 9 additions and 4 deletions
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@ -118,11 +118,11 @@ void Spc::UpdateClockRatio()
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{
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_clockRatio = (double)(Spc::SpcSampleRate * 64) / _console->GetMasterClockRate();
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//If the target cycle is off by more than 10 cycles, reset the counter to match what was expected
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//If the target cycle is off by more than 20 cycles, reset the counter to match what was expected
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//This can happen due to overclocking (which disables the SPC for some scanlines) or if the SPC's
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//internal sample rate is changed between versions (e.g 32000hz -> 32040hz)
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uint64_t targetCycle = (uint64_t)(_memoryManager->GetMasterClock() * _clockRatio);
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if(std::abs((int64_t)targetCycle - (int64_t)_state.Cycle) > 10) {
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if(std::abs((int64_t)targetCycle - (int64_t)_state.Cycle) > 20) {
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_state.Cycle = targetCycle;
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}
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}
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@ -444,12 +444,17 @@ uint8_t* Spc::GetSpcRom()
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void Spc::Serialize(Serializer &s)
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{
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if(s.IsSaving()) {
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//Catch up SPC to main CPU before creating the state
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Run();
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}
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SV(_state.A); SV(_state.Cycle); SV(_state.PC); SV(_state.PS); SV(_state.SP); SV(_state.X); SV(_state.Y);
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SV(_state.CpuRegs[0]); SV(_state.CpuRegs[1]); SV(_state.CpuRegs[2]); SV(_state.CpuRegs[3]);
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SV(_state.OutputReg[0]); SV(_state.OutputReg[1]); SV(_state.OutputReg[2]); SV(_state.OutputReg[3]);
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SV(_state.RamReg[0]); SV(_state.RamReg[1]);
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SV(_state.ExternalSpeed); SV(_state.InternalSpeed); SV(_state.WriteEnabled); SV(_state.TimersEnabled);
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SV(_state.DspReg); SV(_state.RomEnabled); SV(_clockRatio);
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SV(_state.DspReg); SV(_state.RomEnabled); SV(_clockRatio); SV(_state.TimersDisabled);
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s.PushNamePrefix("timer0", -1);
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_state.Timer0.Serialize(s);
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@ -472,7 +477,7 @@ void Spc::Serialize(Serializer &s)
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}
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if(s.GetFormat() != SerializeFormat::Map) {
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SV(_operandA); SV(_operandB); SV(_tmp1); SV(_tmp2); SV(_tmp3); SV(_opCode); SV(_opStep); SV(_opSubStep); SV(_enabled); SV(_state.TimersDisabled);
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SV(_operandA); SV(_operandB); SV(_tmp1); SV(_tmp2); SV(_tmp3); SV(_opCode); SV(_opStep); SV(_opSubStep); SV(_enabled);
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}
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}
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