mirror of
https://github.com/SourMesen/Mesen2.git
synced 2025-04-02 10:21:44 -04:00
204 lines
No EOL
3.2 KiB
JSON
204 lines
No EOL
3.2 KiB
JSON
{
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"instructions": [
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{
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"op": "adc",
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"name": "ADC - Add with Carry",
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"description": ""
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},
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{
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"op": "add",
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"name": "ADD - Add",
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"description": ""
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},
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{
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"op": "and",
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"name": "AND - Bitwise AND",
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"description": ""
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},
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{
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"op": "b",
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"name": "B - Branch",
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"description": ""
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},
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{
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"op": "bal",
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"name": "BAL - Branch Always",
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"description": ""
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},
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{
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"op": "bic",
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"name": "BIC - Bit Clear",
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"description": ""
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},
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{
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"op": "bl",
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"name": "BL - Branch with Link",
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"description": ""
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},
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{
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"op": "bll",
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"name": "BLL - Branch with Link (low)",
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"description": ""
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},
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{
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"op": "blh",
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"name": "BLH - Branch with Link (high)",
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"description": ""
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},
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{
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"op": "bx",
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"name": "BX - Branch and Exchange",
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"description": ""
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},
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{
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"op": "asr",
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"name": "ASL - Arithmetic Shift Right",
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"description": ""
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},
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{
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"op": "cmn",
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"name": "CMN - Compare Negative",
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"description": ""
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},
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{
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"op": "cmp",
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"name": "CMP - Compare",
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"description": ""
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},
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{
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"op": "eor",
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"name": "EOR - Exclusive OR",
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"description": ""
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},
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{
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"op": "ldm",
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"name": "LDM - Load Multiple Registers",
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"description": ""
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},
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{
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"op": "ldr",
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"name": "LDR - Load Register",
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"description": ""
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},
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{
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"op": "lds",
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"name": "LDS - Load Sign-Extended",
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"description": ""
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},
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{
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"op": "lsl",
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"name": "LSL - Logical Shift Left",
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"description": ""
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},
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{
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"op": "lsr",
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"name": "LSR - Logical Shift Right",
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"description": ""
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},
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{
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"op": "mla",
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"name": "MLA - Multiply Accumulate",
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"description": ""
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},
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{
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"op": "mov",
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"name": "MOV - Move",
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"description": ""
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},
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{
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"op": "mrs",
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"name": "MRS - Move Status to Register",
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"description": ""
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},
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{
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"op": "msr",
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"name": "MSR - Move Register to Status",
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"description": ""
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},
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{
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"op": "mul",
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"name": "MUL - Multiply",
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"description": ""
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},
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{
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"op": "mvn",
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"name": "MVN - Move Negative Register",
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"description": ""
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},
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{
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"op": "neg",
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"name": "NEG - Negate",
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"description": ""
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},
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{
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"op": "orr",
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"name": "ORR - Inclusive OR",
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"description": ""
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},
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{
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"op": "pop",
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"name": "POP - Pop Registers",
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"description": ""
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},
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{
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"op": "push",
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"name": "PUSH - Push Registers",
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"description": ""
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},
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{
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"op": "ror",
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"name": "ROR - Rotate Right",
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"description": ""
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},
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{
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"op": "rsb",
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"name": "RSB - Reverse Subtract",
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"description": ""
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},
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{
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"op": "rsc",
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"name": "RSC - Reverse Subtract with Carry",
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"description": ""
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},
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{
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"op": "sbc",
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"name": "SBC - Subtract with Carry",
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"description": ""
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},
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{
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"op": "stm",
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"name": "STM - Store Multiple Registers",
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"description": ""
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},
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{
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"op": "str",
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"name": "STR - Store Register",
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"description": ""
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},
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{
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"op": "sub",
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"name": "SUB - Subtract",
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"description": ""
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},
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{
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"op": "swi",
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"name": "SWI - Software Interrupt",
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"description": ""
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},
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{
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"op": "swp",
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"name": "SWP - Swap Register with Memory",
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"description": ""
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},
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{
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"op": "teq",
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"name": "TEQ - Test Equality",
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"description": ""
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},
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{
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"op": "tst",
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"name": "TST - Test Bits",
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"description": ""
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}
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]
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} |