mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
c275218a89
accordance to the newboot document: * reset vector (16 bytes) * vpd (240bytes) * boot block (8k - 256b) * lar archive (256-8 k) The boot block is kind of simple, still. It enables pmode, car, and starts looking for an initram module in the lar archive. Note: This doesnt do much at the moment, as gas seems to produce buggy code in init.S. Take this as a suggestion of how it might work and please provide patches fixing it and bringing it into shape. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@62 f3766cd6-281f-0410-b1cd-43a5c92072e9
259 lines
6.1 KiB
ArmAsm
259 lines
6.1 KiB
ArmAsm
/* Copyright (C) 2005 Eswar Nallusamy, LANL
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* Copyright (C) 2005 Yinghai Lu, Tyan Corp.
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* Copyright (C) 2007 Stefan Reinauer, coresystems GmbH
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/* We will use 4Kbytes only for cache as ram. This is
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* enough to fit in our stack.
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*
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* disable HyperThreading is done by eswar
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* the other is very similar to the AMD CAR, except remove amd specific msr
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*/
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#define CacheSize 4096
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#define CacheBase (0xd0000 - CacheSize)
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#define ASSEMBLY
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#include "mtrr.h"
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/* Save the BIST result */
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movl %eax, %ebp
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CacheAsRam:
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/* Check whether the processor has HT capability */
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movl $01, %eax
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cpuid
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btl $28, %edx
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jnc NotHtProcessor
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bswapl %ebx
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cmpb $01, %bh
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jbe NotHtProcessor
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/* It is a HT processor; Send SIPI to the other logical processor
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* within this processor so that the CAR related common system
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* registers are programmed accordingly
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*/
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/* Use some register that is common to both logical processors
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* as semaphore. Refer Appendix B, Vol.3
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*/
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xorl %eax, %eax
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xorl %edx, %edx
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movl $0x250, %ecx
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wrmsr
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/* Figure out the logical AP's APIC ID; the following logic will work
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* only for processors with 2 threads.
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*
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* Refer to Vol 3. Table 7-1 for details about this logic
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*/
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movl $0xFEE00020, %esi
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movl (%esi), %ebx
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andl $0xFF000000, %ebx
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bswapl %ebx
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btl $0, %ebx
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jnc LogicalAP0
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andb $0xFE, %bl
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jmp SendSIPI
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LogicalAP0:
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orb $0x01, %bl
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SendSIPI:
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bswapl %ebx /* ebx - logical AP's APIC ID */
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/* Fill up the IPI command registers in the Local APIC mapped to
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* default address and issue SIPI to the other logical processor
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* within this processor die.
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*/
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RetrySIPI:
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movl %ebx, %eax
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movl $0xFEE00310, %esi
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movl %eax, (%esi)
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/* SIPI vector - F900:0000 */
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movl $0x000006F9, %eax
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movl $0xFEE00300, %esi
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movl %eax, (%esi)
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movl $0x30, %ecx
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SIPIDelay:
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pause
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decl %ecx
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jnz SIPIDelay
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movl (%esi), %eax
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andl $0x00001000, %eax
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jnz RetrySIPI
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/* Wait for the Logical AP to complete initialization */
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LogicalAPSIPINotdone:
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movl $0x250, %ecx
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rdmsr
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orl %eax, %eax
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jz LogicalAPSIPINotdone
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NotHtProcessor:
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/* Set the default memory type and enable fixed and variable MTRRs */
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movl $MTRRdefType_MSR, %ecx
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xorl %edx, %edx
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/* Enable Variable and Fixed MTRRs */
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movl $0x00000c00, %eax
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wrmsr
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/*Clear all MTRRs */
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xorl %edx, %edx
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movl $fixed_mtrr_msr, %esi
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clear_fixed_var_mtrr:
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lodsl (%esi), %eax
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testl %eax, %eax
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jz clear_fixed_var_mtrr_out
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movl %eax, %ecx
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xorl %eax, %eax
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wrmsr
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jmp clear_fixed_var_mtrr
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clear_fixed_var_mtrr_out:
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#if CacheSize == 0x10000
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/* enable caching for 64K using fixed mtrr */
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movl $0x268, %ecx /* fix4k_c0000*/
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movl $0x06060606, %eax /* WB IO type */
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movl %eax, %edx
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wrmsr
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movl $0x269, %ecx
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wrmsr
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#endif
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#if CacheSize == 0x8000
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/* enable caching for 32K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_c8000*/
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movl $0x06060606, %eax /* WB IO type */
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movl %eax, %edx
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wrmsr
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#endif
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/* enable caching for 16K/8K/4K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_cc000*/
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#if CacheSize == 0x4000
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movl $0x06060606, %edx /* WB IO type */
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#endif
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#if CacheSize == 0x2000
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movl $0x06060000, %edx /* WB IO type */
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#endif
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#if CacheSize == 0x1000
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movl $0x06000000, %edx /* WB IO type */
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#endif
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xorl %eax, %eax
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wrmsr
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#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
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/* enable write base caching so we can do execute in place
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* on the flash rom.
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*/
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movl $0x202, %ecx
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xorl %edx, %edx
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movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
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wrmsr
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movl $0x203, %ecx
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movl $0x0000000f, %edx
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movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
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wrmsr
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#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
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/* enable cache */
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movl %cr0, %eax
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andl $0x9fffffff,%eax
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movl %eax, %cr0
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/* Read the range with lodsl*/
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movl $CacheBase, %esi
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cld
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movl $(CacheSize>>2), %ecx
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rep lodsl
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/* Clear the range */
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movl $CacheBase, %edi
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movl $(CacheSize>>2), %ecx
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xorl %eax, %eax
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rep stosl
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#if 0
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/* check the cache as ram */
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movl $CacheBase, %esi
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movl $(CacheSize>>2), %ecx
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.xin1:
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movl %esi, %eax
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movl %eax, (%esi)
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decl %ecx
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je .xout1
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add $4, %esi
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jmp .xin1
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.xout1:
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movl $CacheBase, %esi
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// movl $(CacheSize>>2), %ecx
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movl $4, %ecx
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.xin1x:
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movl %esi, %eax
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movl $0x4000, %edx
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movb %ah, %al
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.testx1:
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outb %al, $0x80
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decl %edx
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jnz .testx1
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movl (%esi), %eax
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cmpb 0xff, %al
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je .xin2 /* dont show */
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movl $0x4000, %edx
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.testx2:
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outb %al, $0x80
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decl %edx
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jnz .testx2
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.xin2: decl %ecx
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je .xout1x
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add $4, %esi
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jmp .xin1x
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.xout1x:
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#endif
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movl $(CacheBase+CacheSize-4), %eax
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movl %eax, %esp
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/* Load a different set of data segments */
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movw $CACHE_RAM_DATA_SEG, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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lout:
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/* Restore the BIST result */
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movl %ebp, %eax
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/* We need to set ebp ? No need */
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movl %esp, %ebp
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pushl %eax /* bist */
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call stage1_main
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/* We will not go back */
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fixed_mtrr_msr:
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.long 0x250, 0x258, 0x259
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.long 0x268, 0x269, 0x26A
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.long 0x26B, 0x26C, 0x26D
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.long 0x26E, 0x26F
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var_mtrr_msr:
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.long 0x200, 0x201, 0x202, 0x203
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.long 0x204, 0x205, 0x206, 0x207
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.long 0x208, 0x209, 0x20A, 0x20B
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.long 0x20C, 0x20D, 0x20E, 0x20F
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.long 0x000 /* NULL, end of table */
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