mirror of
https://github.com/fail0verflow/switch-coreboot.git
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f28a44eb48
image, and fails: LAR build/coreboot.rom Bootblock coreboot.bootblock does not appear to be a bootblock. Error adding the bootblock to the LAR. make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error 1 Next step is to get rid of all warnings that are not #warning. Then it is on to simnow. Anyone who wants to work on the warnings is most welcome to. DBE62 still builds with no problems. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@808 f3766cd6-281f-0410-b1cd-43a5c92072e9
106 lines
3.1 KiB
C
106 lines
3.1 KiB
C
/*
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* AMD 8111 "southbridge"
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* This file is part of the coreboot project.
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* Copyright (C) 2004-2005 Linux Networx
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* (Written by Eric Biederman <ebiederman@lnxi.com> and Jason Schildt for Linux Networx)
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* Copyright (C) 2005-7 YingHai Lu
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* Copyright (C) 2005 Ollie Lo
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* Copyright (C) 2005-2007 Stefan Reinauer <stepan@openbios.org>
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/pci.h>
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#include <msr.h>
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#include <legacy.h>
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#include <device/pci_ids.h>
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#include <statictree.h>
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#include <config.h>
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#include "amd8111.h"
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void amd8111_enable(struct device * dev)
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{
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struct device * lpc_dev;
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struct device * bus_dev;
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unsigned index;
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unsigned reg_old, reg;
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/* See if we are behind the amd8111 pci bridge */
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bus_dev = dev->bus->dev;
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if ((bus_dev->id.pci.vendor == PCI_VENDOR_ID_AMD) &&
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(bus_dev->id.pci.device == PCI_DEVICE_ID_AMD_8111_PCI))
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{
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unsigned devfn;
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devfn = bus_dev->path.pci.devfn + (1 << 3);
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lpc_dev = dev_find_slot(bus_dev->bus->secondary, devfn);
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index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
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if (dev->path.pci.devfn == 2) { /* EHCI */
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index = 16;
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}
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} else {
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unsigned devfn;
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devfn = (dev->path.pci.devfn) & ~7;
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lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
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index = dev->path.pci.devfn & 7;
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}
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if ((!lpc_dev) || (index >= 17)) {
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return;
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}
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if ((lpc_dev->id.pci.vendor != PCI_VENDOR_ID_AMD) ||
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(lpc_dev->id.pci.device != PCI_DEVICE_ID_AMD_8111_ISA))
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{
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u32 id;
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id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
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if (id != (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8111_ISA << 16))) {
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return;
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}
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}
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if (index < 16) {
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reg = reg_old = pci_read_config16(lpc_dev, 0x48);
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reg &= ~(1 << index);
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if (dev->enabled) {
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reg |= (1 << index);
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}
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if (reg != reg_old) {
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pci_write_config16(lpc_dev, 0x48, reg);
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}
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}
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else if (index == 16) {
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reg = reg_old = pci_read_config8(lpc_dev, 0x47);
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reg &= ~(1 << 7);
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if (!dev->enabled) {
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reg |= (1 << 7);
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}
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if (reg != reg_old) {
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pci_write_config8(lpc_dev, 0x47, reg);
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}
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}
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}
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struct device_operations amd8111 = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_8111_PCI}}},
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.constructor = default_device_constructor,
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.phase3_scan = 0,
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.phase4_enable_disable = amd8111_enable,
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.phase4_read_resources = pci_dev_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase6_init = NULL,
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.ops_pci = &pci_dev_ops_pci,
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};
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