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1b22622323
The individual makefiles in lib/ mainboard/ southbridge/ and superio/ have been changed accordingly and the big glue layer in arch/x86Makefile has been modified to wrap the new rules correctly. This pepares the way for additional optimizations during compile and link time. Build tested and boot tested on Qemu. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@782 f3766cd6-281f-0410-b1cd-43a5c92072e9
32 lines
1.1 KiB
Makefile
32 lines
1.1 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007 coresystems GmbH
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## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y)
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STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/cs5536.c
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ifeq ($(CONFIG_PIRQ_TABLE),y)
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STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/irq_tables.c
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endif
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STAGE0_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/stage1.c
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endif
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