switch-coreboot/southbridge
Ronald G. Minnich 9cdd8a9d67 This finishes the fix to log2. The computed dram size now matches the
size indicated by byte 31 of SPD. 

Memory is still not working; hanging in dqs training. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@854 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-01 02:44:08 +00:00
..
amd This finishes the fix to log2. The computed dram size now matches the 2008-09-01 02:44:08 +00:00
intel/i82371eb Minor cosmetic and/or license header fixes (trivial). 2008-08-11 21:01:54 +00:00
nvidia/mcp55 Missing include. 2008-08-24 17:10:25 +00:00