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https://github.com/fail0verflow/switch-coreboot.git
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version, with these typos, compiled. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@889 f3766cd6-281f-0410-b1cd-43a5c92072e9
175 lines
5 KiB
C
175 lines
5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2007 AMD
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* (Written by Yinghai Lu <yinghai.lu@amd.com> for AMD)
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* Copyright (C) 2007 Ward Vandewege <ward@gnu.org>
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* Copyright (C) 2008 Peter Stuge <peter@stuge.se>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <io.h>
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#include <lib.h>
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#include <device/device.h>
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#include <device/pnp.h>
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#include <console.h>
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#include <string.h>
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#include <uart8250.h>
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#include <keyboard.h>
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#include <statictree.h>
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#include "it8716f.h"
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/* Base address 0x2e: 0x87 0x01 0x55 0x55. */
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/* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
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static void pnp_enter_ext_func_mode(struct device *dev)
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{
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outb(0x87, dev->path.pnp.port);
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outb(0x01, dev->path.pnp.port);
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outb(0x55, dev->path.pnp.port);
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if (dev->path.pnp.port == 0x4e) {
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outb(0xaa, dev->path.pnp.port);
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} else {
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outb(0x55, dev->path.pnp.port);
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}
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}
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static void pnp_exit_ext_func_mode(struct device *dev)
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{
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pnp_write_config(dev, 0x02, 0x02);
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}
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#ifdef HAVE_FANCTL
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extern void init_ec(u16 base);
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#else
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static void pnp_write_index(u16 port_base, u8 reg, u8 value)
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{
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outb(reg, port_base);
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outb(value, port_base + 1);
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}
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static u8 pnp_read_index(u16 port_base, u8 reg)
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{
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outb(reg, port_base);
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return inb(port_base + 1);
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}
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static void init_ec(u16 base)
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{
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u8 value;
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/* Read out current value of FAN_CTL control register (0x14). */
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value = pnp_read_index(base, 0x14);
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printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\r\n",
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base + 0x14, value);
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/* Set FAN_CTL control register (0x14) polarity to high, and
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activate fans 1, 2 and 3. */
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pnp_write_index(base, 0x14, value | 0x87);
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printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n",
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base + 0x14, value | 0x87);
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}
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#endif
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static void it8716f_pnp_set_resources(struct device *dev)
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{
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pnp_enter_ext_func_mode(dev);
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pnp_set_resources(dev);
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pnp_exit_ext_func_mode(dev);
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}
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static void it8716f_pnp_enable_disable(struct device *dev)
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{
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pnp_enter_ext_func_mode(dev);
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pnp_enable_resources(dev);
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pnp_exit_ext_func_mode(dev);
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}
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static void it8716f_pnp_enable_resources(struct device *dev)
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{
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pnp_enter_ext_func_mode(dev);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, dev->enabled);
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pnp_exit_ext_func_mode(dev);
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}
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static void it8716f_init(struct device *dev)
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{
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struct superio_ite_it8716f_dts_config *conf;
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struct resource *res0, *res1;
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struct pc_keyboard kbd;
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if (!dev->enabled)
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return;
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conf = dev->device_configuration;
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/* TODO: FDC, PP, KBCM, MIDI, GAME, IR. */
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switch (dev->path.pnp.device) {
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case IT8716F_SP1:
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res0 = find_resource(dev, PNP_IDX_IO0);
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// init_uart8250(res0->base, &conf->com1);
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break;
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case IT8716F_SP2:
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res0 = find_resource(dev, PNP_IDX_IO0);
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// init_uart8250(res0->base, &conf->com2);
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break;
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case IT8716F_EC:
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res0 = find_resource(dev, PNP_IDX_IO0);
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#define EC_INDEX_PORT 5
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init_ec(res0->base + EC_INDEX_PORT);
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break;
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case IT8716F_KBCK:
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res0 = find_resource(dev, PNP_IDX_IO0);
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res1 = find_resource(dev, PNP_IDX_IO1);
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init_pc_keyboard(res0->base, res1->base, &kbd);
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break;
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}
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}
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static void it8716f_setup_scan_bus(struct device *dev);
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struct device_operations it8716f_ops = {
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.phase2_setup_scan_bus = it8716f_setup_scan_bus,
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.phase4_read_resources = pnp_read_resources,
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.phase4_set_resources = it8716f_pnp_set_resources,
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.phase4_enable_disable = it8716f_pnp_enable_disable,
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.phase5_enable_resources = it8716f_pnp_enable_resources,
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.phase6_init = it8716f_init,
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};
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static struct pnp_info pnp_dev_info[] = {
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{&it8716f_ops, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
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{&it8716f_ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
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{&it8716f_ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
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{&it8716f_ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
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{&it8716f_ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0},
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{0x7f8, 0x4},},
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{&it8716f_ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0},
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{0x7ff, 0x4},},
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{&it8716f_ops, IT8716F_KBCM, PNP_IRQ0,},
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{&it8716f_ops, IT8716F_GPIO, PNP_IO1 | PNP_IO2, {0, 0}, {0x7f8, 0}, {0x7f8, 0},},
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{&it8716f_ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},},
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{&it8716f_ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},},
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{&it8716f_ops, IT8716F_IR,},
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};
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static void it8716f_setup_scan_bus(struct device *dev)
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{
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pnp_enable_devices(dev, &it8716f_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
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}
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