mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
8e09de297f
We found some boards are not stable when sdram is run at 933Mhz.
Before we can fix it, we need to lower the sdram frequency to 800MHz.
In this patch we modify the DQS delay from 0x280 to 0x260 and extend
the DQS window.
BRANCH=None
BUG=chrome-os-partner:56940
TEST=Booted Kevin.
Change-Id: I68561c4aa4d9ab66acfa3515a42d696157aff759
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 877a7f6ad2
Original-Change-Id: I5eab6bbe96f0dae095c5353403292022e7a25421
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/382724
Original-Commit-Ready: Douglas Anderson <dianders@chromium.org>
Original-Tested-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/16709
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
78 lines
1.7 KiB
C
78 lines
1.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <boardid.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <gpio.h>
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#include <soc/sdram.h>
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#include <string.h>
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#include <types.h>
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static const char *sdram_configs[] = {
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"sdram-lpddr3-hynix-4GB-200",
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"sdram-lpddr3-hynix-4GB-666",
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"sdram-lpddr3-hynix-4GB-800",
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"sdram-lpddr3-hynix-4GB-666-no-odt",
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"sdram-lpddr3-hynix-4GB-800-no-odt",
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"sdram-lpddr3-hynix-4GB-933",
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};
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static struct rk3399_sdram_params params;
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enum dram_speeds {
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dram_200MHz = 0,
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dram_666MHz = 1,
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dram_800MHz = 2,
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dram_666MHz_NO_ODT = 3,
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dram_800MHz_NO_ODT = 4,
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dram_933MHz = 5,
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};
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static enum dram_speeds get_sdram_index(void)
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{
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uint32_t id;
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id = board_id();
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if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN))
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switch (id) {
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case 0:
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case 1:
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case 2:
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return dram_200MHz;
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case 3:
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return dram_666MHz_NO_ODT;
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default:
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return dram_800MHz;
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}
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if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU))
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switch (id) {
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case 0:
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return dram_800MHz_NO_ODT;
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default:
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return dram_800MHz;
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}
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}
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const struct rk3399_sdram_params *get_sdram_config()
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{
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if (cbfs_boot_load_struct(sdram_configs[get_sdram_index()],
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¶ms, sizeof(params)) != sizeof(params))
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die("Cannot load SDRAM parameter file!");
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return ¶ms;
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}
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