Marc Jones b8562cfb7b One missed function rename in the stage2 pci resources allocation. phase4_assign_resources is now phase4_set_resources. (trivial) ... Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1117 f3766cd6-281f-0410-b1cd-43a5c92072e9		2009-01-20 00:03:11 +00:00
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amd	This patch adds reserved regions to the geode northbridge for the ROM and	2009-01-08 20:07:21 +00:00
intel	Port r3747, r3732, r3733 from v2 to v3 (build-tested on v3):	2009-01-08 16:14:12 +00:00
via/cn700	One missed function rename in the stage2 pci resources allocation. phase4_assign_resources is now phase4_set_resources. (trivial)	2009-01-20 00:03:11 +00:00