mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
481e85860b
Peter has some valid points that need to be addressed in the future. See his Ack message. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1100 f3766cd6-281f-0410-b1cd-43a5c92072e9
62 lines
2 KiB
C
62 lines
2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2004 Tyan Computer
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* by yhlu@tyan.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <statictree.h>
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#include "ck804.h"
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static void usb1_init(struct device *dev)
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{
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struct southbridge_nvidia_ck804_usb_config const *conf = dev->device_configuration;
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if (conf->usb1_hc_reset) {
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/*
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* Somehow the warm reset does not really reset the USB
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* controller. Later, during boot, when the Bus Master bit is
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* set, the USB controller trashes the memory, causing weird
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* misbehavior. Was detected on Sun Ultra40, where mptable
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* was damaged.
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*/
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u32 bar0 = pci_read_config32(dev, 0x10);
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u32 *regs = (u32 *) (bar0 & ~0xfff);
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/* OHCI USB HCCommandStatus Register, HostControllerReset bit */
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regs[2] |= 1;
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}
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}
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struct device_operations ck804_usb_ops = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
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.device = PCI_DEVICE_ID_NVIDIA_CK804_USB}}},
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.phase3_chip_setup_dev = ck804_enable,
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.phase3_scan = NULL,
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.phase4_read_resources = pci_dev_read_resources,
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.phase4_set_resources = pci_set_resources,
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.phase5_enable_resources = pci_dev_enable_resources,
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.phase6_init = usb1_init,
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.ops_pci = &ck804_ops_pci,
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};
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