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https://github.com/fail0verflow/switch-coreboot.git
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44d1585458
It's all REV_F now and we're wasting time pretending otherwise. This change simplifies the code and will continue to simplify the code. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@788 f3766cd6-281f-0410-b1cd-43a5c92072e9
235 lines
6.3 KiB
C
235 lines
6.3 KiB
C
/*
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* K8 northbridge
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* This file is part of the coreboot project.
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* Copyright (C) 2004-2005 Linux Networx
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* (Written by Eric Biederman <ebiederman@lnxi.com> and Jason Schildt for Linux Networx)
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* Copyright (C) 2005-7 YingHai Lu
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* Copyright (C) 2005 Ollie Lo
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* Copyright (C) 2005-2007 Stefan Reinauer <stepan@openbios.org>
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
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*/
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/* This should be done by Eric
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2004.12 yhlu add dual core support
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2005.01 yhlu add support move apic before pci_domain in MB Config.lb
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2005.02 yhlu add e0 memory hole support
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2005.11 yhlu add put sb ht chain on bus 0
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*/
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#include <config.h>
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#include <console.h>
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#include <lib.h>
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#include <string.h>
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#include <mtrr.h>
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#include <macros.h>
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#include <spd.h>
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#include <cpu.h>
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#include <msr.h>
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#include <amd/k8/k8.h>
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#include <amd/k8/sysconf.h>
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#include <device/pci.h>
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#include <device/hypertransport_def.h>
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#include <device/hypertransport.h>
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#include <mc146818rtc.h>
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#include <lib.h>
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#include <lapic.h>
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static unsigned int cpu_bus_scan(struct device * dev, unsigned int max)
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{
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struct bus *cpu_bus;
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struct device * dev_mc;
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int bsp_apicid;
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int i,j;
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unsigned nb_cfg_54;
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unsigned siblings;
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int e0_later_single_core;
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int disable_siblings;
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nb_cfg_54 = 0;
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sysconf.enabled_apic_ext_id = 0;
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sysconf.lift_bsp_apicid = 0;
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siblings = 0;
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/* Find the bootstrap processors apicid */
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bsp_apicid = lapicid();
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sysconf.apicid_offset = bsp_apicid;
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disable_siblings = !CONFIG_LOGICAL_CPUS;
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#if CONFIG_LOGICAL_CPUS == 1
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get_option(&disable_siblings, "dual_core");
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#endif
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// for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0)
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// How can I get the nb_cfg_54 of every node' nb_cfg_54 in bsp??? and differ d0 and e0 single core
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nb_cfg_54 = read_nb_cfg_54();
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dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
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if (!dev_mc) {
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die("0:18.0 not found?");
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}
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sysconf.nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1;
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if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
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{
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sysconf.enabled_apic_ext_id = 1;
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if(bsp_apicid == 0) {
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/* bsp apic id is not changed */
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sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET;
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} else
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{
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sysconf.lift_bsp_apicid = 1;
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}
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}
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/* Find which cpus are present */
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cpu_bus = &dev->link[0];
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for(i = 0; i < sysconf.nodes; i++) {
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struct device * dev, *cpu;
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struct device_path cpu_path;
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/* Find the cpu's pci device */
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dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
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if (!dev) {
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/* If I am probing things in a weird order
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* ensure all of the cpu's pci devices are found.
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*/
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int j;
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struct device * dev_f0;
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for(j = 0; j <= 3; j++) {
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dev = pci_probe_dev(NULL, dev_mc->bus,
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PCI_DEVFN(0x18 + i, j));
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}
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/* Ok, We need to set the links for that device.
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* otherwise the device under it will not be scanned
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*/
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dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0));
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if(dev_f0) {
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dev_f0->links = 3;
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for(j=0;j<3;j++) {
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dev_f0->link[j].link = j;
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dev_f0->link[j].dev = dev_f0;
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}
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}
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}
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#warning clean this mess up
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e0_later_single_core = 0;
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if (dev && dev->enabled) {
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j = pci_read_config32(dev, 0xe8);
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j = (j >> 12) & 3; // dev is func 3
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printk(BIOS_DEBUG, " %s siblings=%d\n", dev_path(dev), j);
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if(nb_cfg_54) {
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// For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
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// ----> you can mixed single core e0 and dual core e0 at any sequence
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// That is the typical case
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if(j == 0 ){
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e0_later_single_core = 1; // we are all f0 or later now. is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
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} else {
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e0_later_single_core = 0;
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}
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if(e0_later_single_core) {
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printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\r\n");
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j=1;
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}
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if(siblings > j ) {
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}
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else {
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siblings = j;
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}
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} else {
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siblings = j;
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}
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}
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unsigned jj;
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if(e0_later_single_core || disable_siblings) {
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jj = 0;
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} else
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{
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jj = siblings;
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}
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#if 0
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jj = 0; // if create cpu core1 path in amd_siblings by core0
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#endif
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for (j = 0; j <=jj; j++ ) {
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/* Build the cpu device path */
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cpu_path.type = DEVICE_PATH_APIC;
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cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
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/* See if I can find the cpu */
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cpu = find_dev_path(cpu_bus, &cpu_path);
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/* Enable the cpu if I have the processor */
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if (dev && dev->enabled) {
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/* this is a CPU */
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struct device_id did;
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did.type = DEVICE_ID_CPU;
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#warning fill cpuid; right now it is zero
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if (!cpu) {
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cpu = alloc_dev(cpu_bus, &cpu_path, &did);
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}
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if (cpu) {
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cpu->enabled = 1;
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}
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}
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/* Disable the cpu if I don't have the processor */
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if (cpu && (!dev || !dev->enabled)) {
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cpu->enabled = 0;
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}
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/* Report what I have done */
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if (cpu) {
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cpu->path.apic.node_id = i;
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cpu->path.apic.core_id = j;
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if(sysconf.enabled_apic_ext_id) {
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if(sysconf.lift_bsp_apicid) {
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cpu->path.apic.apic_id += sysconf.apicid_offset;
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} else
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{
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if (cpu->path.apic.apic_id != 0)
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cpu->path.apic.apic_id += sysconf.apicid_offset;
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}
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}
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printk(BIOS_DEBUG, "CPU: %s %s\n",
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dev_path(cpu), cpu->enabled?"enabled":"disabled");
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}
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} //j
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}
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return max;
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}
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static void cpu_bus_init(struct device * dev)
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{
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/* unclear if we need this any more. CPUs are in the device tree. */
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// initialize_cpus(&dev->link[0]);
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//so what do we do? This is a first for v3.
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}
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static void cpu_bus_noop(struct device * dev)
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{
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}
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