mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
4110e67004
Continue to upgrade northbridge for k8. Add a new standard include (which is optional on some chipsets), mainboard.h, which will define important mainboard constants that 1. do not belong in dts 2. do not belong in Kconfig 3. are so tightly tied down to the mainboard they should probably not be visible, i.e. the value of the variable is defined by artwork on the mainboard, such as the socket type. This file resolves the long-standing question of where certain mainboard-dependent, compile-time control variables belong. We've not resolved this issue in two years so here's how we're going to do it. The first use of this is in the definition of CPU_SOCKET_TYPE, needed by the northbridge code. These changes do not affect existing Geode builds (tested on DBE62). Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@792 f3766cd6-281f-0410-b1cd-43a5c92072e9
290 lines
11 KiB
Makefile
290 lines
11 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2006-2007 coresystems GmbH
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## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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## Copyright (C) 2007-2008 Carl-Daniel Hailfinger
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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ifeq ($(CONFIG_ARCH_X86),y)
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INITCFLAGS := $(CFLAGS) -I$(src)/include/arch/x86 -I$(src)/include \
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-I$(obj) -I$(src)/mainboard/$(MAINBOARDDIR)/-fno-builtin
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SILENT := >/dev/null 2>&1
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#
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# Build the ROM Image / LAR archive
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#
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# coreboot v3 is completely modular. One module, the bootblock (stage0),
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# is mandatory. All modules are packed together in a LAR archive.
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# The LAR archive may contain any number of stages, payloads and option ROMs.
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#
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ROM_SIZE := $(shell expr $(CONFIG_COREBOOT_ROMSIZE_KB) \* 1024)
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LARFILES_NOCOMPRESS := coreboot.initram:normal/initram option_table:normal/option_table
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LARFILES_COMPRESSIBLE := coreboot.stage2:normal/stage2
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COMPRESSFLAG :=
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ifeq ($(CONFIG_DEFAULT_COMPRESSION_LZMA),y)
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COMPRESSFLAG := -C lzma
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endif
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ifeq ($(CONFIG_DEFAULT_COMPRESSION_NRV2B),y)
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COMPRESSFLAG := -C nrv2b
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endif
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$(obj)/coreboot.rom $(obj)/coreboot.map: $(obj)/coreboot.bootblock $(obj)/util/lar/lar lzma nrv2b $(obj)/coreboot.initram $(obj)/coreboot.stage2 $(obj)/option_table
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$(Q)printf " LAR $(subst $(shell pwd)/,,$(@))\n"
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$(Q)rm -f $(obj)/coreboot.rom
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$(Q)cd $(obj) && \
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./util/lar/lar -e -c coreboot.rom \
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-s $(ROM_SIZE) -b coreboot.bootblock \
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$(LARFILES_NOCOMPRESS)
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$(Q)cd $(obj) && \
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./util/lar/lar -e $(COMPRESSFLAG) -a coreboot.rom \
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$(LARFILES_COMPRESSIBLE)
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ifeq ($(CONFIG_PAYLOAD_NONE),y)
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$(Q)printf " PAYLOAD none (as specified by user)\n"
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else
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$(Q)if [ -r $(CONFIG_PAYLOAD_FILE) ]; then \
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printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) $(COMPRESSFLAG)\n"; \
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else \
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printf "Error: payload file '$(CONFIG_PAYLOAD_FILE)' not found.\n"; \
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exit 1; \
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fi
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$(Q)$(obj)/util/lar/lar $(PARSEELF) $(COMPRESSFLAG) -a \
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$(obj)/coreboot.rom $(CONFIG_PAYLOAD_FILE):normal/payload;
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endif
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ifeq ($(CONFIG_ZERO_AFTER_PAYLOAD),y)
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$(Q)printf " ZEROING lar -z ./coreboot.rom\n"
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$(Q)cd $(obj) && ./util/lar/lar -z ./coreboot.rom
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endif
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$(Q)# QEMU wants bios.bin:
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$(Q)# Run "qemu -L build/ -serial stdio -hda /dev/zero".
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$(Q)printf " CP $(subst $(shell pwd)/,,$(obj)/bios.bin)\n"
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$(Q)cp $@ $(obj)/bios.bin
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$(Q)echo "Coreboot ROM Image:" > $(obj)/coreboot.map
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$(Q)$(obj)/util/lar/lar -l $(obj)/coreboot.rom >> $(obj)/coreboot.map
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$(Q)(echo; echo "Stage 0/1 Map:") >> $(obj)/coreboot.map
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$(Q)cat $(obj)/stage0.init.map >> $(obj)/coreboot.map
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$(Q)(echo; echo "Stage Initram Map:") >> $(obj)/coreboot.map
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$(Q)cat $(obj)/coreboot.initram.map >> $(obj)/coreboot.map
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$(Q)(echo; echo "Stage 2 Map:") >> $(obj)/coreboot.map
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$(Q)cat $(obj)/coreboot.stage2.map >> $(obj)/coreboot.map
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$(obj)/coreboot.bootblock: $(obj)/coreboot.vpd $(obj)/stage0.init
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$(Q)printf " BUILD $(subst $(shell pwd)/,,$(@))\n"
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$(Q)cat $^ > $@
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#
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# Coreboot stage0. This is the coreboot "boot block code".
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# It enables Cache-as-RAM and parses the LAR archive for an
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# initram module and the various stages and payload files.
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#
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STAGE0_LIB_SRC = uart8250.c mem.c lar.c delay.c vtxprintf.c \
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vsprintf.c console.c string.c $(DECOMPRESSORS)
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STAGE0_ARCH_X86_SRC = stage1.c serial.c speaker.c \
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udelay_io.c mc146818rtc.c post_code.c \
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pci_ops_conf1.c resourcemap.c
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ifeq ($(CONFIG_PAYLOAD_ELF_LOADER),y)
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STAGE0_LIB_SRC += elfboot.c
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STAGE0_ARCH_X86_SRC += archelfboot.c
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endif
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ifeq ($(CONFIG_CPU_I586),y)
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STAGE0_CAR_OBJ = stage0_i586.o
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else
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ifeq ($(CONFIG_CPU_AMD_GEODELX),y)
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STAGE0_CAR_OBJ = geodelx/stage0.o
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STAGE0_ARCH_X86_SRC += geodelx/stage1.c
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STAGE0_ARCH_X86_SRC += ../../northbridge/amd/geodelx/geodelxinit.c
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else
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ifeq ($(CONFIG_CPU_AMD_K8),y)
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STAGE0_CAR_OBJ = amd/stage0.o
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STAGE0_ARCH_X86_SRC += amd/k8/stage1.c
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endif
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endif
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endif
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ifeq ($(CONFIG_PAYLOAD_NO_PREPARSE_ELF), y)
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PARSEELF =
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else
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PARSEELF = -e
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endif
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STAGE0_SRC := $(patsubst %,$(src)/lib/%,$(STAGE0_LIB_SRC)) \
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$(patsubst %,$(src)/arch/x86/%,$(STAGE0_ARCH_X86_SRC)) \
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$(STAGE0_MAINBOARD_SRC) $(STAGE0_CHIPSET_SRC)
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STAGE0_OBJ := $(patsubst $(src)/%.c,$(obj)/%.o,$(STAGE0_SRC)) \
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$(patsubst %,$(obj)/arch/x86/%,$(STAGE0_CAR_OBJ))
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$(obj)/stage0.o $(obj)/stage0.init $(obj)/stage0-prefixed.o: $(STAGE0_OBJ)
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$(Q)# We need to be careful. If stage0.o gets bigger than
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$(Q)# 0x4000 - 0x100, we will end up with a 4 gig file.
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$(Q)# I wonder if that behavior is on purpose.
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$(Q)# .data and .bss must be empty because they aren't handled
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$(Q)printf " CHECK stage0 (non-empty writable/allocatable sections)\n"
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$(Q)./util/sectionchecker/sectionchecker objdump readelf $(STAGE0_OBJ)
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$(Q)# Note: we invoke gcc (instead of ld directly) here, as we hit
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$(Q)# strange problems in the past. It seems that only gcc knows how
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$(Q)# to properly invoke ld.
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$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(CC) -nostdlib -static -T $(src)/arch/x86/ldscript.ld \
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$(STAGE0_OBJ) -o $(obj)/stage0.o
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$(Q)printf " OBJCOPY $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(OBJCOPY) -O binary $(obj)/stage0.o $(obj)/stage0.init
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$(Q)# Do another OBJCOPY to get a copy with renamed symbols
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$(Q)# for XIP code.
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$(Q)printf " OBJCOPY $(subst $(shell pwd)/,,$(@)) (prefixing stage0)\n"
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$(Q)$(OBJCOPY) --prefix-symbols=stage0_ $(obj)/stage0.o $(obj)/stage0-prefixed.o
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$(Q)printf " TEST $(subst $(shell pwd)/,,$(@))\n"
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$(Q)test `wc -c < $(obj)/stage0.init` -gt 20224 && \
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printf "Error. Bootblock got too big.\n" || true
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$(Q)printf " NM $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(NM) $(obj)/stage0.o | sort -u > $(obj)/stage0.init.map
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#
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# This is the rest of coreboot (v2: coreboot_ram.rom).
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# Is this maybe platform independent, except for the "drivers"?
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# Where should it be built, maybe in device/?
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#
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# TODO: This should be compressed with the default compressor.
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#
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STAGE2_LIB_SRC = stage2.c clog2.c mem.c tables.c delay.c \
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compute_ip_checksum.c string.c
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STAGE2_ARCH_X86_SRC = archtables.c coreboot_table.c udelay_io.c
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STAGE2_ARCH_X86_SRC += pci_ops_auto.c
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STAGE2_ARCH_X86_SRC += keyboard.c i8259.c isa-dma.c
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ifeq ($(CONFIG_PIRQ_TABLE),y)
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STAGE2_ARCH_X86_SRC += pirq_routing.c
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endif
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STAGE2_DYNAMIC_SRC = $(obj)/mainboard/$(MAINBOARDDIR)/statictree.c
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STAGE2_SRC := $(patsubst %,$(src)/lib/%,$(STAGE2_LIB_SRC)) \
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$(patsubst %,$(src)/arch/x86/%,$(STAGE2_ARCH_X86_SRC)) \
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$(patsubst %,$(src)/device/%,$(STAGE2_DEVICE_SRC)) \
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$(patsubst %,$(src)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_SRC))
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STAGE2_SRC += $(STAGE2_CHIPSET_SRC)
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STAGE2_OBJ := $(patsubst $(src)/%.c,$(obj)/%.o,$(STAGE2_SRC))
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# This one is special because the static tree object ends up in the mainboard
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# dir of the object tree.
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STAGE2_OBJ += $(patsubst $(obj)/%.c,$(obj)/%.o,$(STAGE2_DYNAMIC_SRC))
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ifeq ($(CONFIG_PCI_OPTION_ROM_RUN),y)
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ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y)
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# x86emu wants libgcc
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ifneq ($(strip $(CC)),)
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LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)
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endif
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endif
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STAGE2_OBJ += $(obj)/util/x86emu/libx86emu.a $(LIBGCC_FILE_NAME)
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endif
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# To reduce code duplication, always make sure STAGE2_OBJ does not contain
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# any object from STAGE0_OBJ.
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STAGE2_OBJ_NEEDED = $(filter-out $(STAGE0_OBJ), $(STAGE2_OBJ))
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$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.o $(STAGE2_OBJ_NEEDED) $(STAGE2_SRC)
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$(Q)# leave a .o with full symbols in it for debugging.
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$(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x2000 --entry=stage2 \
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-o $(obj)/coreboot.stage2 $(STAGE2_OBJ_NEEDED)
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$(Q)$(NM) $(obj)/coreboot.stage2 | sort -u > $(obj)/coreboot.stage2.map
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#
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# Build rules.
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#
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$(obj)/arch/x86/%.o: $(src)/arch/x86/%.c
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$(Q)mkdir -p $(dir $@)
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$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(CC) $(INITCFLAGS) -c $< -o $@
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# Building asm stub.
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$(obj)/arch/x86/stage0%.o: $(src)/arch/x86/stage0%.S
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$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(CC) -E $(COREBOOTINCLUDE) $< \
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-o $(obj)/arch/x86/stage0_asm.s -DBOOTBLK=0x1f00 \
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-DRESRVED=0xf0 -DDATE=\"`date +%Y/%m/%d`\"
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$(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@
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$(obj)/arch/x86/geodelx/stage0.o: $(src)/arch/x86/geodelx/stage0.S
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$(Q)mkdir -p $(dir $@)
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$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(CC) -E $(COREBOOTINCLUDE) $< \
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-o $(obj)/arch/x86/stage0_asm.s -DBOOTBLK=0x1f00 \
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-DRESRVED=0xf0 -DDATE=\"`date +%Y/%m/%d`\"
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$(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@
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# NOTE HACK. Stefan will fix this :-)
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$(obj)/arch/x86/amd/stage0.o: $(src)/arch/x86/amd/stage0.S
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$(Q)mkdir -p $(dir $@)
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$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(CC) -E $(COREBOOTINCLUDE) $< \
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-I $(src)/include/arch/x86/amd/k8 \
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-o $(obj)/arch/x86/stage0_asm.s -DBOOTBLK=0x1f00 \
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-DRESRVED=0xf0 -DDATE=\"`date +%Y/%m/%d`\"
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$(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@
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$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_SRC)
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$(Q)printf " CC $(subst $(shell pwd)/,,$(@)) (XIP)\n"
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$(Q)$(CC) $(INITCFLAGS) -fPIE -c -combine $(INITRAM_SRC) -o $(obj)/coreboot.initram_partiallylinked.o
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$(Q)# .data and .bss must be empty because they aren't handled
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$(Q)printf " CHECK initram (non-empty writable/allocatable sections)\n"
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$(Q)./util/sectionchecker/sectionchecker objdump readelf $(obj)/coreboot.initram_partiallylinked.o
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$(Q)printf " WRAP $(subst $(shell pwd)/,,$(@)) (PIC->non-PIC)\n"
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$(Q)$(NM) --undefined-only $(obj)/coreboot.initram_partiallylinked.o |\
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grep -v _GLOBAL_OFFSET_TABLE_ | grep " U " | sed "s/^ *U //" |\
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$(src)/util/picwrapper/picwrapper > $(obj)/initram_picwrapper.s
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$(Q)printf " AS initram_picwrapper.s\n"
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$(Q)$(AS) $(obj)/initram_picwrapper.s -o $(obj)/initram_picwrapper.o
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$(Q)# initram links against stage0
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$(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \
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$(obj)/coreboot.initram_partiallylinked.o \
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$(obj)/initram_picwrapper.o -o $(obj)/coreboot.initram
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$(Q)printf " NM $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(NM) $(obj)/coreboot.initram | sort -u > $(obj)/coreboot.initram.map
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endif
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