mirror of
https://github.com/fail0verflow/switch-coreboot.git
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30c0db46ed
it working, then we'll get it pretty. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@717 f3766cd6-281f-0410-b1cd-43a5c92072e9
405 lines
12 KiB
C
405 lines
12 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2006-2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define ROM_CODE_SEG 0x08
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#define ROM_DATA_SEG 0x10
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#define CACHE_RAM_CODE_SEG 0x18
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#define CACHE_RAM_DATA_SEG 0x20
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#define IORR_FIRST 0xC0010016
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#define IORR_LAST 0xC0010019
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#define MTRR_READ_MEM (1 << 4)
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#define MTRR_WRITE_MEM (1 << 3)
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#define SYSCFG_MSR 0xC0010010
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#define SYSCFG_MSR_TOM2En (1 << 21)
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#define SYSCFG_MSR_MtrrVarDramEn (1 << 20)
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#define SYSCFG_MSR_MtrrFixDramModEn (1 << 19)
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#define SYSCFG_MSR_MtrrFixDramEn (1 << 18)
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#define SYSCFG_MSR_UcLockEn (1 << 17)
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#define SYSCFG_MSR_ChxToDirtyDis (1 << 16)
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#define SYSCFG_MSR_ClVicBlkEn (1 << 11)
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#define SYSCFG_MSR_SetDirtyEnO (1 << 10)
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#define SYSCFG_MSR_SetDirtyEnS (1 << 9)
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#define SYSCFG_MSR_SetDirtyEnE (1 << 8)
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#define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5))
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#define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0))
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#define IORR0_BASE 0xC0010016
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#define IORR0_MASK 0xC0010017
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#define IORR1_BASE 0xC0010018
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#define IORR1_MASK 0xC0010019
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#define TOP_MEM 0xC001001A
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#define TOP_MEM2 0xC001001D
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#define TOP_MEM_MASK 0x007fffff
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#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
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/* Definitions of various K8 registers */
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/* Function 0 */
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#define HT_TRANSACTION_CONTROL 0x68
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#define HTTC_DIS_RD_B_P (1 << 0)
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#define HTTC_DIS_RD_DW_P (1 << 1)
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#define HTTC_DIS_WR_B_P (1 << 2)
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#define HTTC_DIS_WR_DW_P (1 << 3)
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#define HTTC_DIS_MTS (1 << 4)
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#define HTTC_CPU1_EN (1 << 5)
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#define HTTC_CPU_REQ_PASS_PW (1 << 6)
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#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
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#define HTTC_DIS_P_MEM_C (1 << 8)
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#define HTTC_DIS_RMT_MEM_C (1 << 9)
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#define HTTC_DIS_FILL_P (1 << 10)
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#define HTTC_RSP_PASS_PW (1 << 11)
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#define HTTC_CHG_ISOC_TO_ORD (1 << 12)
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#define HTTC_BUF_REL_PRI_SHIFT 13
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#define HTTC_BUF_REL_PRI_MASK 3
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#define HTTC_BUF_REL_PRI_64 0
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#define HTTC_BUF_REL_PRI_16 1
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#define HTTC_BUF_REL_PRI_8 2
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#define HTTC_BUF_REL_PRI_2 3
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#define HTTC_LIMIT_CLDT_CFG (1 << 15)
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#define HTTC_LINT_EN (1 << 16)
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#define HTTC_APIC_EXT_BRD_CST (1 << 17)
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#define HTTC_APIC_EXT_ID (1 << 18)
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#define HTTC_APIC_EXT_SPUR (1 << 19)
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#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
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#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
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#define HTTC_DS_NP_REQ_LIMIT_MASK 3
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#define HTTC_DS_NP_REQ_LIMIT_NONE 0
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#define HTTC_DS_NP_REQ_LIMIT_1 1
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#define HTTC_DS_NP_REQ_LIMIT_4 2
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#define HTTC_DS_NP_REQ_LIMIT_8 3
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#define HTTC_MED_PRI_BYP_CNT_SHIFT 24
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#define HTTC_MED_PRI_BYP_CNT_MASK 3
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#define HTTC_HI_PRI_BYP_CNT_SHIFT 26
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#define HTTC_HI_PRI_BYP_CNT_MASK 3
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/* Function 1 */
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#define PCI_IO_BASE0 0xc0
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#define PCI_IO_BASE1 0xc8
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#define PCI_IO_BASE2 0xd0
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#define PCI_IO_BASE3 0xd8
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#define PCI_IO_BASE_VGA_EN (1 << 4)
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#define PCI_IO_BASE_NO_ISA (1 << 5)
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/* Function 2 */
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#define DRAM_CSBASE 0x40
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#define DRAM_CSMASK 0x60
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#define DRAM_BANK_ADDR_MAP 0x80
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#define DRAM_TIMING_LOW 0x88
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#define DTL_TCL_SHIFT 0
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#define DTL_TCL_MASK 0x7
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#define DTL_CL_2 1
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#define DTL_CL_3 2
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#define DTL_CL_2_5 5
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#define DTL_TRC_SHIFT 4
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#define DTL_TRC_MASK 0xf
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#define DTL_TRC_BASE 7
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#define DTL_TRC_MIN 7
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#define DTL_TRC_MAX 22
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#define DTL_TRFC_SHIFT 8
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#define DTL_TRFC_MASK 0xf
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#define DTL_TRFC_BASE 9
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#define DTL_TRFC_MIN 9
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#define DTL_TRFC_MAX 24
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#define DTL_TRCD_SHIFT 12
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#define DTL_TRCD_MASK 0x7
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#define DTL_TRCD_BASE 0
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#define DTL_TRCD_MIN 2
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#define DTL_TRCD_MAX 6
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#define DTL_TRRD_SHIFT 16
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#define DTL_TRRD_MASK 0x7
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#define DTL_TRRD_BASE 0
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#define DTL_TRRD_MIN 2
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#define DTL_TRRD_MAX 4
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#define DTL_TRAS_SHIFT 20
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#define DTL_TRAS_MASK 0xf
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#define DTL_TRAS_BASE 0
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#define DTL_TRAS_MIN 5
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#define DTL_TRAS_MAX 15
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#define DTL_TRP_SHIFT 24
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#define DTL_TRP_MASK 0x7
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#define DTL_TRP_BASE 0
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#define DTL_TRP_MIN 2
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#define DTL_TRP_MAX 6
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#define DTL_TWR_SHIFT 28
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#define DTL_TWR_MASK 0x1
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#define DTL_TWR_BASE 2
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#define DTL_TWR_MIN 2
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#define DTL_TWR_MAX 3
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#define DRAM_TIMING_HIGH 0x8c
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#define DTH_TWTR_SHIFT 0
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#define DTH_TWTR_MASK 0x1
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#define DTH_TWTR_BASE 1
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#define DTH_TWTR_MIN 1
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#define DTH_TWTR_MAX 2
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#define DTH_TRWT_SHIFT 4
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#define DTH_TRWT_MASK 0x7
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#define DTH_TRWT_BASE 1
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#define DTH_TRWT_MIN 1
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#define DTH_TRWT_MAX 6
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#define DTH_TREF_SHIFT 8
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#define DTH_TREF_MASK 0x1f
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#define DTH_TREF_100MHZ_4K 0x00
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#define DTH_TREF_133MHZ_4K 0x01
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#define DTH_TREF_166MHZ_4K 0x02
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#define DTH_TREF_200MHZ_4K 0x03
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#define DTH_TREF_100MHZ_8K 0x08
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#define DTH_TREF_133MHZ_8K 0x09
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#define DTH_TREF_166MHZ_8K 0x0A
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#define DTH_TREF_200MHZ_8K 0x0B
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#define DTH_TWCL_SHIFT 20
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#define DTH_TWCL_MASK 0x7
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#define DTH_TWCL_BASE 1
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#define DTH_TWCL_MIN 1
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#define DTH_TWCL_MAX 2
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#define DRAM_CONFIG_LOW 0x90
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#define DCL_DLL_Disable (1<<0)
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#define DCL_D_DRV (1<<1)
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#define DCL_QFC_EN (1<<2)
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#define DCL_DisDqsHys (1<<3)
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#define DCL_Burst2Opt (1<<5)
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#define DCL_DramInit (1<<8)
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#define DCL_DualDIMMen (1<<9)
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#define DCL_DramEnable (1<<10)
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#define DCL_MemClrStatus (1<<11)
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#define DCL_ESR (1<<12)
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#define DCL_SRS (1<<13)
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#define DCL_128BitEn (1<<16)
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#define DCL_DimmEccEn (1<<17)
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#define DCL_UnBufDimm (1<<18)
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#define DCL_32ByteEn (1<<19)
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#define DCL_x4DIMM_SHIFT 20
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#define DCL_DisInRcvrs (1<<24)
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#define DCL_BypMax_SHIFT 25
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#define DCL_En2T (1<<28)
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#define DCL_UpperCSMap (1<<29)
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#define DRAM_CONFIG_HIGH 0x94
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#define DCH_ASYNC_LAT_SHIFT 0
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#define DCH_ASYNC_LAT_MASK 0xf
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#define DCH_ASYNC_LAT_BASE 0
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#define DCH_ASYNC_LAT_MIN 0
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#define DCH_ASYNC_LAT_MAX 15
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#define DCH_RDPREAMBLE_SHIFT 8
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#define DCH_RDPREAMBLE_MASK 0xf
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#define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */
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#define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */
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#define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */
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#define DCH_IDLE_LIMIT_SHIFT 16
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#define DCH_IDLE_LIMIT_MASK 0x7
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#define DCH_IDLE_LIMIT_0 0
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#define DCH_IDLE_LIMIT_4 1
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#define DCH_IDLE_LIMIT_8 2
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#define DCH_IDLE_LIMIT_16 3
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#define DCH_IDLE_LIMIT_32 4
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#define DCH_IDLE_LIMIT_64 5
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#define DCH_IDLE_LIMIT_128 6
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#define DCH_IDLE_LIMIT_256 7
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#define DCH_DYN_IDLE_CTR_EN (1 << 19)
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#define DCH_MEMCLK_SHIFT 20
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#define DCH_MEMCLK_MASK 0x7
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#define DCH_MEMCLK_100MHZ 0
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#define DCH_MEMCLK_133MHZ 2
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#define DCH_MEMCLK_166MHZ 5
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#define DCH_MEMCLK_200MHZ 7
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#define DCH_MEMCLK_VALID (1 << 25)
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#define DCH_MEMCLK_EN0 (1 << 26)
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#define DCH_MEMCLK_EN1 (1 << 27)
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#define DCH_MEMCLK_EN2 (1 << 28)
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#define DCH_MEMCLK_EN3 (1 << 29)
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/* Function 3 */
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#define MCA_NB_CONFIG 0x44
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#define MNC_ECC_EN (1 << 22)
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#define MNC_CHIPKILL_EN (1 << 23)
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#define SCRUB_CONTROL 0x58
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#define SCRUB_NONE 0
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#define SCRUB_40ns 1
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#define SCRUB_80ns 2
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#define SCRUB_160ns 3
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#define SCRUB_320ns 4
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#define SCRUB_640ns 5
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#define SCRUB_1_28us 6
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#define SCRUB_2_56us 7
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#define SCRUB_5_12us 8
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#define SCRUB_10_2us 9
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#define SCRUB_20_5us 10
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#define SCRUB_41_0us 11
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#define SCRUB_81_9us 12
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#define SCRUB_163_8us 13
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#define SCRUB_327_7us 14
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#define SCRUB_655_4us 15
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#define SCRUB_1_31ms 16
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#define SCRUB_2_62ms 17
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#define SCRUB_5_24ms 18
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#define SCRUB_10_49ms 19
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#define SCRUB_20_97ms 20
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#define SCRUB_42ms 21
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#define SCRUB_84ms 22
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#define SC_DRAM_SCRUB_RATE_SHFIT 0
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#define SC_DRAM_SCRUB_RATE_MASK 0x1f
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#define SC_L2_SCRUB_RATE_SHIFT 8
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#define SC_L2_SCRUB_RATE_MASK 0x1f
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#define SC_L1D_SCRUB_RATE_SHIFT 16
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#define SC_L1D_SCRUB_RATE_MASK 0x1f
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#define SCRUB_ADDR_LOW 0x5C
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#define SCRUB_ADDR_HIGH 0x60
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#define NORTHBRIDGE_CAP 0xE8
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#define NBCAP_128Bit (1 << 0)
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#define NBCAP_MP (1 << 1)
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#define NBCAP_BIG_MP (1 << 2)
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#define NBCAP_ECC (1 << 3)
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#define NBCAP_CHIPKILL_ECC (1 << 4)
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#define NBCAP_MEMCLK_SHIFT 5
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#define NBCAP_MEMCLK_MASK 3
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#define NBCAP_MEMCLK_100MHZ 3
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#define NBCAP_MEMCLK_133MHZ 2
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#define NBCAP_MEMCLK_166MHZ 1
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#define NBCAP_MEMCLK_200MHZ 0
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#define NBCAP_MEMCTRL (1 << 8)
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/* resources for the routing in the northbridge. These may be family specific;
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* the were in v2.
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*/
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#define RES_DEBUG 0
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#define RES_PCI_IO 0x10
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#define RES_PORT_IO_8 0x22
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#define RES_PORT_IO_32 0x20
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#define RES_MEM_IO 0x40
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#ifndef ASSEMBLY
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/* cpu version -- no support for f0 yet */
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static inline int is_cpu_rev_a0(void)
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{
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return (cpuid_eax(1) & 0xfffef) == 0x0f00;
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}
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static inline int is_cpu_pre_c0(void)
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{
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return (cpuid_eax(1) & 0xfffef) < 0x0f48;
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}
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static inline int is_cpu_c0(void)
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{
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return (cpuid_eax(1) & 0xfffef) == 0x0f48;
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}
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static inline int is_cpu_pre_b3(void)
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{
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return (cpuid_eax(1) & 0xfffef) < 0x0f41;
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}
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static inline int is_cpu_b3(void)
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{
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return (cpuid_eax(1) & 0xfffef) == 0x0f41;
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}
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//AMD_D0_SUPPORT
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static inline int is_cpu_pre_d0(void)
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{
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return (cpuid_eax(1) & 0xfff0f) < 0x10f00;
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}
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static inline int is_cpu_d0(void)
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{
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return (cpuid_eax(1) & 0xfff0f) == 0x10f00;
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}
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//AMD_E0_SUPPORT
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static inline int is_cpu_pre_e0(void)
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{
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return (cpuid_eax(1) & 0xfff0f) < 0x20f00;
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}
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static inline int is_cpu_e0(void)
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{
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return (cpuid_eax(1) & 0xfff00) == 0x20f00;
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}
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/* note: we'd like to have this sysinfo common to all K8, there's no need to
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* have one different kind per different kind of k8 at this point.
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*/
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//#include "raminit.h"
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struct dimm_size {
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u8 per_rank; // it is rows + col + bank_lines + data lines */
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u8 rows;
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u8 col;
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u8 bank; //1, 2, 3 mean 2, 4, 8
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u8 rank;
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} __attribute__((packed));
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struct mem_info { // pernode
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u32 dimm_mask;
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struct dimm_size sz[DIMM_SOCKETS];
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u32 x4_mask;
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u32 x16_mask;
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u32 single_rank_mask;
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u32 page_1k_mask;
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// u32 ecc_mask;
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// u32 registered_mask;
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u8 is_opteron;
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u8 is_registered;
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u8 is_ecc;
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u8 is_Width128;
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u8 memclk_set; // we need to use this to retrieve the mem param
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u8 rsv[3];
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} __attribute__((packed));
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struct link_pair_st {
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struct device * udev;
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u32 upos;
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u32 uoffs;
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struct device * dev;
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u32 pos;
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u32 offs;
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} __attribute__((packed));
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struct sys_info {
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u8 ctrl_present[NODE_NUMS];
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struct mem_info meminfo[NODE_NUMS];
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struct mem_controller ctrl[NODE_NUMS];
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u8 mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail
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u32 tom_k;
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u32 tom2_k;
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u32 mem_base[NODE_NUMS];
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u32 cs_base[NODE_NUMS*8]; //8 cs_idx
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u32 hole_reg[NODE_NUMS]; // can we spare it to one, and put ctrl idx in it
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u8 dqs_delay_a[NODE_NUMS*2*2*9]; //8 node channel 2, direction 2 , bytelane *9
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u8 dqs_rcvr_dly_a[NODE_NUMS*2*8]; //8 node, channel 2, receiver 8
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u32 nodes;
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struct link_pair_st link_pair[16];// enough? only in_conherent
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u32 link_pair_num;
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u32 ht_c_num;
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u32 sbdn;
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u32 sblk;
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u32 sbbusn;
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} __attribute__((packed));
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#endif /* ! ASSEMBLY */
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