mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
2beb0a1bcc
- Code to initialize sdram from C on the l440gx - cache as ram code fro the p6 it works except conflict misses occur with addresses that are not cached so writing to ram does not work. Which makes it to brittle to count on. - Initial implementation of a fallback booting scheme where we can have two copies of linuxbios in rom at once. - Movement of 32 bit entry code from entry16.inc to entry32.inc - Update of all config files so they now also include entry32.inc - Fix for start_stop.c & entry16.inc so I can fairly arbitrarily relocate the 16bit entry code in SMP. - A small number of fixes for warnings
22 lines
520 B
Text
22 lines
520 B
Text
arch i386
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript cpu/i386/entry16.lds
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mainboardinit superio/sis/950/setup_serial.inc
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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northsouthbridge sis/730
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# superio sis/950
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nsuperio sis/950 com1={1} floppy=1 lpt=1
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mainboardinit cpu/p6/earlymtrr.inc
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option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
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option FINAL_MAINBOARD_FIXUP=1
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option HAVE_PIRQ_TABLE=1
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object mainboard.o
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object irq_tables.o
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keyboard pc80
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cpu p5
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cpu p6
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cpu k7
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