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https://github.com/fail0verflow/switch-coreboot.git
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0c10964d8d
Baytrail SoC has a bug where in some cases the DisplayPort can hang leading to a non-working display (it just stays black). To avoid this hang, a patch was introduced in 02/2016 (1c3b1112fa- fsp_baytrail: Fix a possible hanging DisplayPort) but per default not switched on so that each mainboard can decide if it wants to use this patch or not. Recently a new case of this bug was reported by Benoit Sansoni (benoit.sansoni@kontron.com) and he requested to enable this fix per default as it costs him a lot of time to find the cause and even the already available fix in coreboot. To avoid this effort for someone else in the future we can enable this fix per default as no negative side effects are known and it is now tested at Siemens and at Kontron on different mainboards with success. As the goal is to enable this code permanently the config switch is not longer needed and is removed. BUG=none BRANCH=none TEST=none Change-Id: I8865b57dafe5df73e82255367562698b1a0a56b4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id:deed5fbebdOriginal-Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355 Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Original-Reviewed-on: https://review.coreboot.org/18109 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://chromium-review.googlesource.com/428264 Commit-Ready: Aaron Durbin <adurbin@chromium.org>
65 lines
1.9 KiB
Makefile
65 lines
1.9 KiB
Makefile
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2010 Google Inc.
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# Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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# Copyright (C) 2016 Siemens AG
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y)
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subdirs-y += romstage
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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subdirs-y += ../../../cpu/x86/cache
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../lib/fsp
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subdirs-y += fsp
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ramstage-y += memmap.c
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romstage-y += memmap.c
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ramstage-y += tsc_freq.c
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romstage-y += tsc_freq.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
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ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
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ramstage-y += spi.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += spi.c
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ramstage-y += chip.c
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ramstage-y += iosf.c
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romstage-y += iosf.c
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ramstage-y += northcluster.c
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ramstage-y += ramstage.c
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ramstage-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += pmutil.c
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ramstage-y += southcluster.c
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romstage-y += reset.c
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ramstage-y += reset.c
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ramstage-y += cpu.c
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ramstage-y += acpi.c
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ramstage-y += lpe.c
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ramstage-y += lpss.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
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ramstage-y += placeholders.c
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ramstage-y += i2c.c
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ramstage-y += gfx.c
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CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include
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CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
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endif
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