mirror of
https://github.com/fail0verflow/switch-coreboot.git
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305d400a83
disk and attempt to boot a linux kernel. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1087 f3766cd6-281f-0410-b1cd-43a5c92072e9
66 lines
1.9 KiB
C
66 lines
1.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef NORTHBRIDGE_VIA_CN700_CN700_H
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#define NORTHBRIDGE_VIA_CN700_CN700_H
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#include <types.h>
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struct board_info {
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u32 d0f2, d0f3, d0f4, d0f7, d1f0;
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u16 spd_channel0[2];
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};
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void cn700_stage1(void);
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void sdram_set_registers(struct board_info *);
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void sdram_set_spd_registers(struct board_info *);
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void ddr2_sdram_enable(struct board_info *);
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/* VGA stuff */
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#define SR_INDEX 0x3c4
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#define SR_DATA 0x3c5
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#define CRTM_INDEX 0x3b4
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#define CRTM_DATA 0x3b5
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#define CRTC_INDEX 0x3d4
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#define CRTC_DATA 0x3d5
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/* Memory Controller Registers */
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#define RANK0_END 0x40
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#define RANK1_END 0x41
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#define RANK2_END 0x42
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#define RANK3_END 0x43
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#define RANK0_START 0x48
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#define RANK1_START 0x49
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#define RANK2_START 0x4a
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#define RANK3_START 0x4b
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#define DDR_PAGE_CTL 0x69
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#define DRAM_REFRESH_COUNTER 0x6a
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#define DRAM_MISC_CTL 0x6b
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#define CH_A_DQS_OUTPUT_DELAY 0x70
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#define CH_A_MD_OUTPUT_DELAY 0x71
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/* RAM Init Commands */
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#define RAM_COMMAND_NORMAL 0x0
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#define RAM_COMMAND_NOP 0x1
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#define RAM_COMMAND_PRECHARGE 0x2
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#define RAM_COMMAND_MRS 0x3
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#define RAM_COMMAND_CBR 0x4
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#endif
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